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mb/siemens/mc_ehl6: Enable PCIe root ports and clocks

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Configure and enable the PCIe root ports and associated clocks for the
mc_ehl6 mainboard. This is necessary because the PCIe configuration
differs from the mc_ehl2 baseboard.

TEST=Boot into the OS and verify that all expected PCIe devices are
correctly detected.

Change-Id: Ie5ac3d437088d1db08f869317ef3e5712c3baa3e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Uwe Poeche 2025-07-07 16:21:33 +02:00 • committed by Matt DeVillier
commit fc88b62174
1 changed files with 12 additions and 3 deletions
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15
src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
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@ -40,12 +40,12 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
@ -55,11 +55,17 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[4]" = "true"
register "PcieRpLtrDisable[6]" = "true"
# Storage (SDCARD/EMMC) related UPDs
@ -176,7 +182,10 @@ chip soc/intel/elkhartlake
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
device pci 1c.0 on end # RP1 (pcie0 single VC)
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)