erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

src/vc/amd/fsp: fix type 17 DMI info

Browse source 
The TYPE17_DMI_INFO struct in renoir FSP has the SMBIOS 3.2 layout, not
the SMBIOS 3.3 layout. The struct definition in the coreboot code needs
to match the one that the FSP uses when creating the DMI into HOB.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icd45d4e25dcc4a5977deaeba2b178e0b9dd1e453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This commit is contained in:
Felix Held 2025-03-11 21:59:22 +01:00
commit 0ed1529ce3
6 changed files with 12 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
View file

@ -12,6 +12,7 @@
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_3_3_SUPPORT 1
#define SMBIOS_3_2_SUPPORT 1
#define SMBIOS_3_3_SUPPORT 1
#endif /* SOC_DMI_INFO_H */

4
src/vendorcode/amd/fsp/common/dmi_info.h
View file

@ -165,7 +165,7 @@ typedef struct {
OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts
OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts
// SMBIOS 3.2
#ifdef SMBIOS_3_2_3_3_SUPPORT
#ifdef SMBIOS_3_2_SUPPORT
OUT UINT8 MemoryTechnology; ///< Memory technology type for this memory device
OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR MemoryOperatingModeCapability; ///< The operating modes supported by this memory device
OUT CHAR8 FirmwareVersion[10]; ///< String number for the firmware version of this memory device
@ -178,9 +178,11 @@ typedef struct {
OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any.
OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes.
// SMBIOS 3.3
#ifdef SMBIOS_3_3_SUPPORT
OUT UINT32 ExtendedSpeed; ///< Extended Speed
OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
#endif
#endif
} __packed TYPE17_DMI_INFO;
/// Collection of pointers to the DMI records

3
src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
View file

@ -13,6 +13,7 @@
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 31
#define SMBIOS_3_2_3_3_SUPPORT 1
#define SMBIOS_3_2_SUPPORT 1
#define SMBIOS_3_3_SUPPORT 1
#endif /* SOC_DMI_INFO_H */

3
src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
View file

@ -12,6 +12,7 @@
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_3_3_SUPPORT 1
#define SMBIOS_3_2_SUPPORT 1
#define SMBIOS_3_3_SUPPORT 1
#endif /* SOC_DMI_INFO_H */

3
src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
View file

@ -12,6 +12,7 @@
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 21
#define SMBIOS_3_2_3_3_SUPPORT 1
#define SMBIOS_3_2_SUPPORT 1
#define SMBIOS_3_3_SUPPORT 1
#endif /* SOC_DMI_INFO_H */

2
src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
View file

@ -12,6 +12,6 @@
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 21 //TODO check
#define SMBIOS_3_2_3_3_SUPPORT 1
#define SMBIOS_3_2_SUPPORT 1
#endif /* SOC_DMI_INFO_H */