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soc/intel/pantherlake: Add ICC Max and TDC settings for SKU_7

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SKU_7 ICC Max and TDC were not accurate. This commit aligns SKU_7
settings with document #813278 - Panther Lake H Platform Power Map
2.1.1.

Change-Id: Ia66ca5c0d2dc1ba0f0cf3b21476e83923e49969e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jeremy Compostella 2025-11-18 09:21:30 -08:00 • committed by Matt DeVillier
commit 6dbcf903a5
2 changed files with 9 additions and 1 deletions
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3
src/soc/intel/pantherlake/chip.h
View file

@ -76,6 +76,7 @@ enum soc_intel_pantherlake_sku {
PTL_SKU_4,
PTL_SKU_5,
PTL_SKU_6,
PTL_SKU_7,
WCL_SKU_1,
WCL_SKU_2,
WCL_SKU_3,
@ -115,7 +116,7 @@ static const struct soc_intel_pantherlake_power_map {
{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },

7
src/soc/intel/pantherlake/chipset_ptl.cb
View file

@ -71,6 +71,13 @@ chip soc/intel/pantherlake
[VR_DOMAIN_ATOM] = 30 * 4
}"
register "icc_max[PTL_SKU_7]" = "{
[VR_DOMAIN_IA] = 90 * 4,
[VR_DOMAIN_GT] = 56 * 4,
[VR_DOMAIN_SA] = 56 * 4,
[VR_DOMAIN_ATOM] = 30 * 4
}"
register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"