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mb/google/fatcat/var/ruby: Modify usb3 port setting

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Modify usb3 port 0 and 1 settings by vendor's advices.

BUG=b:446771934
TEST=Build and boot to OS, check usb3 functions work by lsusb -t.

Change-Id: I9ed47ead1b2ef0b007897513ceb99e9460875bdc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Luca Lai 2025-11-04 11:01:41 +08:00 • committed by Matt DeVillier
commit 804aab3abb
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/fatcat/variants/ruby/overridetree.cb
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@ -32,8 +32,8 @@ chip soc/intel/pantherlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb3_ports[0]" = "USB3_PORT_EMPTY" # no use
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 Type-A (DB)
register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB)
register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB)
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1