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soc/mediatek: Add Kconfig option MEDIATEK_WDT_RESET_BY_SW

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When the watchdog timeout triggers a reset, the CPU will return to the
default frequency. If there is a mismatch between voltage and frequency,
the device will fail to reboot. Therefore, the kernel configuration
"mediatek,disable-extrst" is removed for MT8189, meaning the watchdog
timeout will trigger external reset, by notifying PMIC and EC via
AP_PMIC_WDTRST_L.

As we want to keep the watchdog status registers until coreboot runs,
the MT8189's EC simply ignores the external reset signal
AP_PMIC_WDTRST_L. Because EC ignores it, coreboot has to trigger the
secondary reset by another method other than watchdog hardware.

Therefore, introduce a Kconfig option MEDIATEK_WDT_RESET_BY_SW to
trigger the secondary reset by board_reset(), which is often implemented
by asserting a GPIO (for example GPIO_AP_EC_WARM_RST_REQ for MT8189).

BUG=b:433636690
TEST=emerge-skywalker coreboot
BRANCH=skywalker

Change-Id: Ib4c698bfd1b85705be05f40f385f4e252975c319
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90172
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
This commit is contained in:
Yu-Ping Wu 2025-10-29 15:15:28 +08:00 • committed by Matt DeVillier
commit 1ae0cebff3
2 changed files with 27 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

9
src/soc/mediatek/common/Kconfig
View file

@ -60,6 +60,15 @@ config MEDIATEK_DSI_CPHY
help
The configuration to support DSI C-PHY.
config MEDIATEK_WDT_RESET_BY_SW
bool
default n
help
This option allows triggering secondary watchdog (WDT) reset by the
software driver, as opposed to by the watchdog hardware.
If the kernel disables WDT external reset (mediatek,disable-extrst),
then this option must be disabled to allow WDT hardware external reset.
config MEMORY_TEST
bool
default y

28
src/soc/mediatek/common/wdt.c
View file

@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <console/console.h>
#include <halt.h>
#include <reset.h>
#include <soc/wdt.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -15,20 +16,27 @@ __weak void mtk_wdt_clear_efuse_ecc(void) { /* do nothing */ }
static inline void mtk_wdt_swreset(void)
{
/*
* We trigger a secondary reset by triggering WDT hardware to send the
* signal to EC.
* We do not use do_board_reset() to send the signal to EC which is
* controlled by software driver.
* Before triggering the secondary reset, clean the data cache so the
* logs in cbmem console (either in SRAM or DRAM) can be flushed.
* We trigger a secondary reset by either do_board_reset() or WDT hardware,
* both of which eventually send the signal to EC.
*/
printk(BIOS_INFO, "%s() called!\n", __func__);
dcache_clean_all();
/* Kick the watchdog to reset timer. */
write32(&mtk_wdt->wdt_restart, MTK_WDT_RESTART_KEY);
setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
udelay(100);
write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
if (CONFIG(MEDIATEK_WDT_RESET_BY_SW)) {
board_reset();
} else {
/*
* Before triggering the secondary reset, clean the data cache so the
* logs in cbmem console (either in SRAM or DRAM) can be flushed.
*/
dcache_clean_all();
setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
udelay(100);
write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
}
halt();
}