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soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C

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The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.

The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8189, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).

Fortunately, the Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is also
enabled. Therefore, even if WATCHDOG_TOMBSTONE data is cleared, the
elog_handle_watchdog_tombstone() function can still obtain the correct
watchdog reset reason from EC.

On MT8189, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8189 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.

Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.

BUG=b:433636690, b:456672760
TEST=emerge-skywalker coreboot
TEST=watchdog event added to eventlog on WDT timeout
TEST=cbmem logs preserved on WDT timeout
BRANCH=skywalker

Change-Id: Id1cfc2700301ebb0b6399356b884b2473c883445
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
This commit is contained in:
Yu-Ping Wu 2025-10-31 15:44:50 +08:00 • committed by Matt DeVillier
commit 7d3bf767cc
1 changed files with 7 additions and 3 deletions
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10
src/soc/mediatek/mt8189/include/soc/memlayout.ld
View file

@ -4,9 +4,12 @@
SECTIONS
{
/* MT8189 has 64KB SRAM. */
/*
* MT8189 has 64KB SRAM. Per HW design, on SoC reset via GPIO
* AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means
* SRAM data will be lost across SoC resets.
*/
SRAM_START(0x00100000)
WATCHDOG_TOMBSTONE(0x00100030, 4)
/*
* MCUPM uses the following regions to exchange data with kernel.
@ -58,7 +61,8 @@ SECTIONS
DMA_COHERENT(0x020DC000, 4K)
STACK(0x020DD000, 15K)
TIMESTAMP(0x020E0C00, 1K)
PRERAM_CBMEM_CONSOLE(0x020E1000, 124K)
PRERAM_CBMEM_CONSOLE(0x020E1000, 123K)
WATCHDOG_TOMBSTONE(0x0020FFC00, 4)
SRAM_L2C_END(0x02100000)
DRAM_START(0x40000000)