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soc/amd/cezanne: Increase APOB DRAM size for Renoir

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The renoir variant has larger APOB data.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b7da3b35f2795deb785f82326f3e6c640f6e9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maximilian Brune 2025-11-10 17:24:41 +01:00 • committed by Felix Held
commit f35cb39de5
4 changed files with 6 additions and 4 deletions
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2
src/mainboard/amd/crater/board_renoir.fmd
View file

@ -6,6 +6,6 @@ FLASH 16M {
PSP_NVRAM(PRESERVE) 128K
PSP_RPMC_NVRAM(PRESERVE) 256K
EC_BODY@15872K 256K
RW_MRC_CACHE 64K
RW_MRC_CACHE 120K
}
}

2
src/mainboard/amd/crater/chromeos_renoir.fmd
View file

@ -30,6 +30,6 @@ FLASH 16M {
SMMSTORE(PRESERVE) 256K
RW_LEGACY(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE(PRESERVE) 64K
RW_MRC_CACHE(PRESERVE) 120K
}
}

2
src/soc/amd/cezanne/Kconfig
View file

@ -157,10 +157,12 @@ config PSP_APOB_DRAM_ADDRESS
config PSP_APOB_DRAM_SIZE
hex
default 0x1E000 if SOC_AMD_RENOIR
default 0x10000
config PSP_SHAREDMEM_BASE
hex
default 0x201F000 if VBOOT && SOC_AMD_RENOIR
default 0x2011000 if VBOOT
default 0x0
help

4
src/soc/amd/cezanne/memmap.c
View file

@ -32,7 +32,7 @@
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
@ -44,7 +44,7 @@
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |