mb/amd/crater: Add XGBE support
If XGBE is used on the platform, it can be configured to match different use cases. Change-Id: Ia6f7c2b836050e52bfb1d9ff64745d83715c874b Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90104 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune
Felix Held
parent
f61553c9fa
commit
bd858faee8
5 changed files with 233 additions and 2 deletions
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@ -112,6 +112,58 @@ config PCIE_DT_SLOT
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endchoice
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choice
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prompt "SGMII lanes interface"
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depends on XGBE_WWAN_WLAN
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default GBE_PATH_SELECT_AIC2
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help
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Option to select either AIC2 card (Marvell Phy), AIC3 card (Broadcom Phy) or
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Backplane mode for SGMII
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config GBE_PATH_SELECT_AIC2
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bool "AIC2 PHY"
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help
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Select to use AIC2 Marvell Phy card
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config GBE_PATH_SELECT_AIC3
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bool "AIC3 PHY"
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help
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Select to use AIC3 Boradcom Phy card
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config XGBE_PATH_SELECT_BACKPLANE
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bool "BackPlane"
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help
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Select to use BackPlane Mode
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endchoice # "SGMII lanes interface"
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choice
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prompt "XGBE port speed"
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depends on XGBE_WWAN_WLAN && !XGBE_PATH_SELECT_BACKPLANE
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default XGBE_10_100_1000MB_SPEED
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config XGBE_10_100_1000MB_SPEED
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bool "10/100/1000MB"
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help
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Set XGBE port speed to support 10/100/1000MB.
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config XGBE_10MB_SPEED
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bool "10MB Port Speed"
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help
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Set XGBE port speed to support 10MBps.
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config XGBE_100MB_SPEED
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bool "100 MBps port speed"
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help
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Set XGBE port speed to support 1000MBps.
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config XGBE_1G_SPEED
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bool "1G Port Speed"
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help
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Set XGBE port speed to support 1GBps.
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endchoice # "XGBE port speed"
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if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
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config EFS_SPI_READ_MODE
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default 3 # Quad IO (1-1-4)
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@ -4,10 +4,12 @@ bootblock-y += bootblock.c
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bootblock-y += early_gpio.c
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bootblock-y += ec.c
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romstage-y += ec.c
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romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c
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ramstage-y += chromeos.c
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ramstage-y += gpio.c
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ramstage-y += ec.c
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ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),)
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@ -106,6 +106,8 @@
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#define ECRAM_BOARDID_OFFSET 0x93
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#define CRATER_REVB 0x42
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#define ECRAM_MACID_OFFSET 0x54
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#define MACID_LEN 12
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static void configure_ec_gpio(void)
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{
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@ -211,3 +213,30 @@ void crater_ec_init(void)
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crater_boardrevision();
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configure_ec_gpio();
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}
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void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac)
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{
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uint64_t port0_mac = 0;
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uint64_t port1_mac = 0;
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uint8_t value = 0;
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uint8_t index = 0;
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uint8_t offset = ECRAM_MACID_OFFSET;
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ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
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for (index = 0; index < MACID_LEN; index++) {
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value = ec_read(offset + index);
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printk(BIOS_SPEW, "READ MACID REG 0x%2x Value 0x%02x\n", offset - index, value);
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if (index < 6) {
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port0_mac = (port0_mac << 8) | value;
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} else {
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port1_mac = (port1_mac << 8) | value;
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}
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}
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printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", port0_mac);
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printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", port1_mac);
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*xgbe_port0_mac = port0_mac;
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*xgbe_port1_mac = port1_mac;
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}
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@ -5,5 +5,6 @@
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void crater_ec_init(void);
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void crater_boardrevision(void);
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void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac);
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#endif /* CRATER_EC_H */
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@ -10,8 +10,8 @@
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#include <ec/acpi/ec.h>
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#include <stdint.h>
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#define ECRAM_MACID_OFFSET 0x54
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#define MACID_LEN 12
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#include <static.h>
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#include "ec.h"
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#define ECRAM_BOARDID_OFFSET 0x93
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@ -200,3 +200,150 @@ void mainboard_get_dxio_ddi_descriptors(
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*ddi_descs = crater_ddi_descriptors;
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*ddi_num = ARRAY_SIZE(crater_ddi_descriptors);
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}
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#if CONFIG(XGBE_PATH_SELECT_BACKPLANE)
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#define xgbe_port0_table_descriptor { \
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.xgbe_port_config = XGBE_PORT_DISABLE, \
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.xgbe_port_connected_type = XGBE_BACKPLANE_CONNECTION, \
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.xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \
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.xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \
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.xgba_port_pad_mdio = 0x0, \
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.xgba_port_pad_i2c = 0x1, \
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.xgbe_port_sfp_tx_fault_gpio = 0xE, \
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.xgbe_port_sfp_rx_los_gpio = 0xD, \
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.xgbe_port_sfp_mod_abs_gpio = 0xC, \
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.xgbe_port_sfp_twi_bus = 0x1, \
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.xgbe_port_mdio_reset_type = 0x0, \
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.xgbe_port_reset_gpio_num = 0x0, \
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.xgbe_port_mdio_reset_i2c_address = 0x0, \
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.xgbe_port_sfp_i2c_address = 0x1, \
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.xgbe_port_sfp_gpio_mask = 0x2, \
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.xgbe_port_sfp_rs_gpio = 0x0, \
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.xgba_port_redriver_model = 0x0, \
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.xgba_port_redriver_interface = 0x1, \
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.xgba_port_redriver_address = 0x0, \
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.xgba_port_redriver_lane = 0x0, \
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.xgbe_port_sfp_twi_address = 0x1C, \
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.xgba_port_pad_gpio = 0x0, \
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.reserve1 = 0x0, \
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.xgbe_port_mdio_id = 0x0, \
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}
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#define xgbe_port1_table_descriptor { \
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.xgbe_port_config = XGBE_PORT_DISABLE, \
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.xgbe_port_connected_type = XGBE_BACKPLANE_CONNECTION, \
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.xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \
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.xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \
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.xgba_port_pad_mdio = 0x0, \
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.xgbe_port_mdio_id = 0x0, \
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.xgba_port_pad_i2c = 0x1, \
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.xgbe_port_sfp_tx_fault_gpio = 0xA, \
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.xgbe_port_sfp_rx_los_gpio = 0x9, \
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.xgbe_port_sfp_mod_abs_gpio = 0x8, \
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.xgbe_port_sfp_twi_bus = 0x2, \
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.xgbe_port_mdio_reset_type = 0x0, \
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.xgbe_port_reset_gpio_num = 0x0, \
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.xgbe_port_mdio_reset_i2c_address = 0x0, \
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.xgbe_port_sfp_i2c_address = 0x1, \
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.xgbe_port_sfp_gpio_mask = 0x2, \
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.xgbe_port_sfp_rs_gpio = 0x0, \
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.xgba_port_redriver_model = 0x0, \
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.xgba_port_redriver_interface = 0x1, \
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.xgba_port_redriver_address = 0x0, \
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.xgba_port_redriver_lane = 0x0, \
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.xgbe_port_sfp_twi_address = 0x1C, \
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.xgba_port_pad_gpio = 0x0, \
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.reserve1 = 0x0, \
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}
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#else
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#define xgbe_port0_table_descriptor { \
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.xgbe_port_config = XGBE_PORT_DISABLE, \
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.xgbe_port_connected_type = XGBE_CONNECTION_MDIO_PHY, \
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.xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \
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.xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED) ? XGBE_PORT_SPEED_1G : \
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CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \
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CONFIG(XGBE_10MB_SPEED) ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \
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.xgba_port_pad_mdio = 0x1, \
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.xgba_port_pad_i2c = 0x0, \
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.xgbe_port_sfp_tx_fault_gpio = 0xB, \
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.xgbe_port_sfp_rx_los_gpio = 0xD, \
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.xgbe_port_sfp_mod_abs_gpio = 0xC, \
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.xgbe_port_sfp_twi_bus = 0x0, \
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.xgbe_port_mdio_reset_type = 0x0, \
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.xgbe_port_reset_gpio_num = 0x0, \
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.xgbe_port_mdio_reset_i2c_address = 0x0, \
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.xgbe_port_sfp_i2c_address = 0x1, \
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.xgbe_port_sfp_gpio_mask = 0x2, \
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.xgbe_port_sfp_rs_gpio = 0x0, \
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.xgba_port_redriver_model = 0x0, \
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.xgba_port_redriver_interface = 0x1, \
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.xgba_port_redriver_address = 0x0, \
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.xgba_port_redriver_lane = 0x0, \
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.xgbe_port_sfp_twi_address = 0x1C, \
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.xgba_port_pad_gpio = 0x0, \
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.reserve1 = 0x0, \
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.xgbe_port_mdio_id = 0x0, \
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}
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#define xgbe_port1_table_descriptor { \
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.xgbe_port_config = XGBE_PORT_DISABLE, \
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.xgbe_port_connected_type = XGBE_CONNECTION_MDIO_PHY, \
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.xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \
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.xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED) ? XGBE_PORT_SPEED_1G : \
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CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \
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CONFIG(XGBE_10MB_SPEED) ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \
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.xgba_port_pad_mdio = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x2 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \
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.xgbe_port_mdio_id = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x0 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \
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.xgba_port_pad_i2c = 0x0, \
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.xgbe_port_sfp_tx_fault_gpio = 0xA, \
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.xgbe_port_sfp_rx_los_gpio = 0x9, \
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.xgbe_port_sfp_mod_abs_gpio = 0x8, \
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.xgbe_port_sfp_twi_bus = 0x1, \
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.xgbe_port_mdio_reset_type = 0x0, \
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.xgbe_port_reset_gpio_num = 0x0, \
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.xgbe_port_mdio_reset_i2c_address = 0x0, \
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.xgbe_port_sfp_i2c_address = 0x1, \
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.xgbe_port_sfp_gpio_mask = 0x2, \
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.xgbe_port_sfp_rs_gpio = 0x0, \
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.xgba_port_redriver_model = 0x0, \
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.xgba_port_redriver_interface = 0x1, \
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.xgba_port_redriver_address = 0x0, \
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.xgba_port_redriver_lane = 0x0, \
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.xgbe_port_sfp_twi_address = 0x1C, \
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.xgba_port_pad_gpio = 0x0, \
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.reserve1 = 0x0, \
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}
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#endif
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static void xgbe_init(FSP_M_CONFIG *mcfg)
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{
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static struct xgbe_port_table xgbe_port[2] = {
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xgbe_port0_table_descriptor,
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xgbe_port1_table_descriptor
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};
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/* MAC can be updated here to pass the same to FSP */
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crater_ec_get_mac_addresses(&mcfg->xgbe_port0_mac, &mcfg->xgbe_port1_mac);
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printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", mcfg->xgbe_port0_mac);
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printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", mcfg->xgbe_port1_mac);
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mcfg->xgbe_port0_config_en = is_dev_enabled(DEV_PTR(xgbe_0));
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mcfg->xgbe_port1_config_en = is_dev_enabled(DEV_PTR(xgbe_1));
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if (mcfg->xgbe_port0_config_en) {
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xgbe_port[0].xgbe_port_config = XGBE_PORT_ENABLE;
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mcfg->xgbe_port0_table = (uint32_t)(uintptr_t)&xgbe_port[0];
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}
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if (mcfg->xgbe_port1_config_en) {
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xgbe_port[1].xgbe_port_config = XGBE_PORT_ENABLE;
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mcfg->xgbe_port1_table = (uint32_t)(uintptr_t)&xgbe_port[1];
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}
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}
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void mb_pre_fspm(FSP_M_CONFIG *mcfg)
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{
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xgbe_init(mcfg);
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}
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