This patch also provides valid 'io_port_mmio_base', which is the addr of
VIRT_FW_CFG device @0x1010_0000 used to convey ACPI & SMBIOS info.
TEST=build and run successfully on QEMU rvvirt machine.
Change-Id: I3cfd3020f1edacbc647188ab232c0a35dbd71f74
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".
Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The 'id' in OTHER_HSL macro is non-typed, downflow would occur when
‘id’ is unsigned and less greater than hart_id. Cast it to int.
Change-Id: I777337b7e374024aff6fb36de603b799b1a65371
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.
This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.
Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled
Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)
Not working:
- S3 sleep
Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to align
with the naming conventions used for other FSP-M configuration
functions.
Change-Id: I0044c21a8f82dfa2308fade78adbd8bcf844cb63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
I found a typo in the comments, so I fixed it.
It seems that 'this operations' is a typographical error.
Change-Id: Ic272e122ce180dee8c0516ecea27cd10932c2363
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PPC64 is not functional without [OPAL] with which Linux kernel
communicates to implement important functionality like a TPM driver.
In addition to providing runtime services via OPAL Skiboot also handles
some parts of the boot process (like extracting kernel from flash) and
adjusts device tree as needed.
coreboot does not currently implement OPAL and is not likely to do it
any time soon (if ever), so must use Skiboot as a second-stage firmware
to have a fully functional PPC64 device.
mb/raptor-cs/talos-2/Kconfig is updated because Skiboot doesn't fit into
512 KiB image.
[OPAL]: https://open-power.github.io/skiboot/doc/opal-spec.html
Change-Id: I49ad6094acaccf731ab6d6b45ac103d485a3179c
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Table is from vendor.
Decrease HWEQ high pass filter from 300Hz to 125Hz.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: Id8f20af4b37cb84ec1720e7c36082c7f8cf9abb1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89284
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.
BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.
Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add support for Class-D Smart Amplifiers: CS35L56, CS35L57 and CS35L63.
CS35L56 and CS35L57 are 18.5 V Class D Smart Amplifiers with Multi-Cell
Battery Boost.
CS35L63 is a PC Smart Amplifier with Speaker Protection and Audio
Enhancement Algorithms.
The driver was written based on the Datasheets for these parts and
generates the audio SSDT information for the amplifiers. Since all
three parts are part of the same family they all have similar SoundWire
settings.
The user can configure which part, SSID and Speaker ID is generated in
ACPI, as well as define each amplifier's Soundwire Unique ID and Link
ID.
These parts support DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.
These parts also support the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.
This is currently only tested using QEMU using example configuration:
chip drivers/soundwire/cs35l56
# SoundWire Link 2 ID 3
register "desc" = ""Left Speaker Amp""
register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
register "sub" = ""12345678""
device generic 2.3 on end
end
Which produces the ACPI:
Device (SW23)
{
Name (_ADR, 0x00023301FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0F)
{
Package (0x02)
{
"mipi-sdw-sw-interface-revision",
0x00010000
},
[...]
Package (0x02)
{
"mipi-sdw-source-port-list",
0x18
},
Package (0x02)
{
"mipi-sdw-sink-port-list",
0x06
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x06)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
},
Package (0x02)
{
"mipi-sdw-dp-0-subproperties",
"DP0"
},
Package (0x02)
{
"mipi-sdw-dp-1-sink-subproperties",
"SNK1"
},
Package (0x02)
{
"mipi-sdw-dp-2-sink-subproperties",
"SNK2"
},
Package (0x02)
{
"mipi-sdw-dp-3-source-subproperties",
"SRC3"
},
Package (0x02)
{
"mipi-sdw-dp-4-source-subproperties",
"SRC4"
}
}
})
Name (BRA0, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x04)
{
Package (0x02)
{
"mipi-sdw-bra-mode-min-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-data-per-frame",
0x01D6
},
Package (0x02)
{
"mipi-sdw-bra-mode-min-us-between-transactions",
Zero
}
}
})
Name (DP0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x07)
{
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x01)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
}
}
})
Name (SNK1, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0C)
{
Package (0x02)
{
"mipi-sdw-data-port-type",
Zero
},
Package (0x02)
{
"mipi-sdw-max-grouping-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-imp-def-dpn-interrupts-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-modes-supported",
One
},
Package (0x02)
{
"mipi-sdw-max-async-buffer",
Zero
},
Package (0x02)
{
"mipi-sdw-block-packing-mode",
One
},
Package (0x02)
{
"mipi-sdw-port-encoding-type",
One
},
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
Package (0x02)
{
"mipi-sdw-simplified-channelprepare-sm",
Zero
},
Package (0x02)
{
"mipi-sdw-port-channelprepare-timeout",
Zero
},
Package (0x02)
{
"mipi-sdw-channel-number-list",
Package (0x02)
{
Zero,
One
}
},
Package (0x02)
{
"mipi-sdw-channel-combination-list",
Package (0x01)
{
0x03
}
}
}
})
Name (SNK2, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC3, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC4, Package (0x02)
{
[... same as SNK1 ...]
})
}
Change-Id: Ie04020f008862051f26e0101828b5944d212e706
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boardview shows the COM port header is connected to serial port A on the
super I/O chip while serial port B pins are unconnected, but it has been
coded for serial port B which cannot be correct.
Change to initialize serial port A instead.
This aligns it with other variants in the family, allowing it
to take advantage of future bootblock code unification.
Change-Id: I8c1a46bef7d9c89f423f8fea9a826b9549d783b4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found on many Asus P8x7x series mainboards, NCT5535D is a 64-pin LPC
super I/O chip with no publicly available datasheet. However, it appears
to share the same silicon as NCT6779D. With only half the pins of 6779,
it does not have parallel port, serial port B, or GPIOs 1 and 6.
This patch adds header and Kconfig option for 5535, and adapts 6779
code to also supply C code to 5535 as well.
asus/p8z77-v_lx2 still builds once modified for this chip, but is not
tested further.
Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds long overdue power loss resume support to nct6779d using
code from nct5572d.
Change-Id: I91bf01a176716b97c6ca6a841c68cd3d4a39d23d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88701
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f3211e9639 ("soc/intel/pantherlake: Add support for Acoustic
Noise Mitigation UPDs") introduced minor coding convention
violations. These are being addressed as follows:
- Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to
align with the naming conventions used for other FSP-M configuration
functions.
- Removes an unnecessary empty line.
- Aligns function parameters.
Change-Id: I8652c2fee71c8e2742146b5e622633de78c1c17e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89332
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Enable External bypass config2 for kaladin and keep FIVR settings for kelsier, and set vccin_aux_imon_iccmax to PD_TIER_VOLUME based on intel
team suggestion.
BUG=b:445829422
TEST=build and flash to DUT, check suspend_stress_test -c 1 pass
Cq-Depend:chrome-internal:8601618
Change-Id: I79e4f61c4bef9b628756a882c8d8dc0a9cb2238c
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89276
Reviewed-by: Doris <doris.hsu@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add the FW_CONFIG configuration for the Padme project of audio amp
and set up I2S for CS35L51.
BUG=b:422688421
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=Skywalker
Change-Id: I3486561dcc8695d3d3585c4844654bb7c68a2979
Signed-off-by: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Set the RTC EOSC (External Oscillator) calibration to 8 seconds in
rtc_boot flow to ensure the accuracy of the RTC time during long period
of suspend. Without this setting, default value is 0, meaning no EOSC
calibration.
BRANCH=rauru
BUG=b:441304060
TEST=emerge-rauru coreboot chromeos-bootimage, when suspend/
warmboot/coldboot, RTC boots and works normally.
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Change-Id: Ia7f15a6056cfa6bd808bc5a91147c1d64aff1223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.
Change-Id: I0b4a1ad351a5772059061837a32d3d8a08c43885
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89283
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated by util/vboot_list/vboot_list.sh.
Change-Id: I313b9a59b9a009257fa4a0969c91b334feb55b8b
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89354
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This adds the release notes template for the upcoming December release
of coreboot.
Change-Id: Iffaa625137f4edf994d73984d847b1cf926f8078
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Explain when the MBOX_PSP return codes are send and which behaviour
is invoked by the PSP when seeing such return codes.
Change-Id: Ibe7ceb5d7cd025f3b3ab0c9167d23f6eb664c165
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When coreboot is operating on the SPI flash lock the bus by
setting SPI_SEMAPHORE_BIOS_LOCKED in SPI_MISC_CNTRL. This prevents
SMM from accidentally corrupting SPI CTRL registers, even though
SMM backups and restores SPI CTRL registers.
TEST: Booted an AMD glinda and observed SMM not accessing the SPI
controller as long as ring 0 is operating on it.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaeda356b55d3f203c75f4056da7bde2abacebc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently the PSP SMI handler works only if you are lucky. Since
ring 0 can start SPI flash transactions any time and the PSP SMI might
happen shortly after that, the SPI controller or SPI flash might be
busy. When the SPI flash is busy it cannot process certain commands,
for example reading the contents, causing the SPI flash memory map
to return all 0xffs.
By introducing the AMD fTPM code the PSP SMI happens more often at
boot and uncovered this issue. This issue was found when deleting
the MRC cache, which takes quite long, while the PSP SMI tried to
access the SPI flash. Adding small delays, as introduced by
CONSOLE_SERIAL, resolved the issue.
Add code to check if the SPI controller and the SPI flash are busy.
If so tell the PSP SMI to retry at a later point in time.
TEST: AMD glinda boots with CONSOLE_SERIAL disabled.
Logging to CBMEM shows that the PSP SMI is fired 10 times
before the SPI flash no longer reports that it's busy.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9122165e7c60b7c288d5b61b80d4cb582901841c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for MIPI panel on padme and enable TM_TL121BVMS07_00C as
the default panel. The panel uses AW37503 as the bias IC, with supply
set to ±5.9V. Add AW37503 initialization and power-on sequence are
configured according to the specification.
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
BUG=b:432353024
TEST=emerge-skywalker coreboot
Change-Id: I37a1c0352a8619ce5b10727cdeef524ccb1107ef
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89218
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the schematic diagram of lapis, refer to
the design of fatcat and modify the gpio order of mem_id.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I715634e231725bbd009b35a0c520d19a894f569c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Add HYNIX H54G46CYRBX267 as id 1, and add Samsung K3KLALA0EM-MGCU
as id 2, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
BUG=b:438785495
TEST=Use part_id_gen to generate related settings
Change-Id: I4179e31222d461b93f81c784511cc34071c10257
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This CL follow Commit 2ba74b8c18 ("mb/google/brox: Hint romstage init
about upcoming reset") CB:84937 to add PDC FW hash in variant.c to hint
romstage init about upcoming reset.
BUG=b:445606386
TEST=Build Caboc BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ie029bf7faf991f520c42ffe22e610291ba98e078
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89190
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently check_auxfw_ver_mismatch() expects the hash file to contain
only auxiliary firmware version and hence strictly checks for the size
of the auxiliary firmware version (3 bytes).
However, in some cases the hash file might contain other information
such as config_name.bin name which increases the hash file size.
Accommodate this scenario by checking the hash file size greater than
or equal to auxiliary firmware version size.
BUG=b:445606386
TEST=Build BIOS image with hash size of 3 and 11. Ensure that the
hints are provided correctly and 2 redundant resets are filtered out.
Change-Id: I287079cfc3cfbc75575ecde0603b98c57b42aa24
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Adds the `google_chromeec_ap_poweroff()` helper function to the ChromeEC
driver.
This new API wraps the `EC_CMD_AP_SHUTDOWN` command and sends it to the
Embedded Controller (EC). This provides a cleaner, standardized way for
other coreboot components to initiate an Application Processor (AP)
power-off sequence via the EC.
After sending the shutdown command, the function calls `halt()` as the
AP is expected to power down immediately after the EC processes the
command.
BUG=b:439819922
TEST=Verify shutdown on Google/Quenbi.
Change-Id: Iace6a66972791bb7acdb978dfeea67b6ff0fec68
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89223
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
60aa7ccea9c include/ec_commands.h: Avoid lint errors
The original include/ec_cmd_api.h version in the EC repo is:
f47d8af4fbb include/ec_cmd_api.h: Define new API for EC_CMD_AP_SHUTDOWN command
Change-Id: I31d08bf4a0318ca3ba8c5bb5563acfe65830523b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit updates the DDR5 memory initialization parameters for the
Intel PTLRVP mainboard. Specifically, the ChannelToCkdQckMapping and
PhyClockToCkdDimm settings are overridden to ensure accurate mapping of
memory channels and PHY clocks to their respective Clock Driver and
DIMM connections.
BUG=none
TEST=Boot the PTLRVP board with DDR5 memory and verify memory
initialization.
Change-Id: I1be0a66a40e2613f10426dacd5494e345c5579db
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change allows flag to be overridden via devicetree, instead of
relying on the default value in alc711_slave. It helps fix the
missing event issue when plugging or unplugging the 3.5mm headphone
jack.
TEST=Verified build and boot with ALC721.
Headphone path switches successfully via audio jack event.
Change-Id: Ib766363fd7462bb03905fa6cba805b27d10efa04
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88867
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic diagram, lapis is designed
with five temperature detection nodes, so the initial
thermal strategy was updated.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change corrects the ACPI wake event mapping for the gspi0 device,
ensuring the wake signal is routed through GPE0_DW2_19 instead of
GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in
devicetree.cb
Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The list of changes are as follows
1. Modified USB2 port 7 from M.2 WLAN to discrete Bluetooth device.
2. Updated both Type-C ports to OC_SKIP to reflect virtual ports.
3. Adjusted Type-C port ACPI group assignments for USB3 ports.
4. Reduced display device count from 5 to 4 by removing DD04.
5. Updated comments and port usage to clarify Type-A and Type-C port
assignments.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I1e8cc92463a462c9baa78cd6d79637004340f7e2
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The FP_PRESENT probe is not required for the ISH device as they are not
in the same BDF. ISH is in the rootport 0:18:0 and gspi0 is 0:30:2.
Change-Id: I00ee0825f60719fb5a34a215780a14645def8b4c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Use fw config bit 15 to identify different ish files when enable
or disable tablet mode.
TABLET_ENABLE : pujjolo_ish.bin
TABLET_DISABLE : lite_ish.bin
BUG=b:432649211
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version
and test warmboot/coldboot/suspend pass.
Change-Id: Iffaadd5c772be6306cdcec08385de90c089f0489
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89215
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).
The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.
The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.
w/o this patch
```
[ERROR] Unable to load previous training data.
```
w/ this patch
```
[WARN ] qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```
Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Ocelot uses the CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
because the hardware does not have DRAM ID straps, but this option was
designed for boards that would only ever have a single memory option.
In order to support multiple memory parts, we need to create a table
that maps memory part number to DRAM id so that we can select the
correct SPD for the memory, and then override the variant_memory_sku()
routine so that we can determine and return the correct DRAM id for
the memory part number specified in the CBI.
BUG=b:443646405
TEST=Change DRAM part number in CBI to "H58G66BK7BX067", reboot ocelot
and verify the AP boot logs show that the SPD index = 1.
Change-Id: I18ba6c4891c6053f40e99dcde8a06b9efc1d95f4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit updates the PCIe root port configuration for the SD card
interface in the overridetree.cb file for the Ocelot variant.
The reference is changed from `pcie_rp5` to `pcie_rp6`.
BUG=b:440042829
TEST=Boot the device with the updated firmware and verify that the
SD card is enumerated under pcie_rp6
Change-Id: I2b3c0b6e19409fef933aa7dc06f5df035f620738
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88873
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to build for PantherLake with TME disabled, key generation
needs to depend on TME Kconfig.
Change-Id: I0af438e279f422292302387442489bcbc1b1605f
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89226
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
