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drivers/emulation/qemu: Adjust fw_cfg driver for Arm and RISCV

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According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.

TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".

Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Ziang Wang 2025-09-25 16:09:42 +08:00 • committed by Matt DeVillier
commit ba3f529681
1 changed files with 14 additions and 3 deletions
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17
src/drivers/emulation/qemu/fw_cfg.c
View file

@ -11,10 +11,17 @@
#include <device/fw_cfg.h>
#include <device/fw_cfg_if.h>
#if CONFIG(ARCH_ARM) || CONFIG(ARCH_RISCV)
#define FW_CFG_PORT_CTL 0x08
#define FW_CFG_PORT_DATA 0x00
#define FW_CFG_DMA_ADDR_HIGH 0x10
#define FW_CFG_DMA_ADDR_LOW 0x14
#else
#define FW_CFG_PORT_CTL 0x0510
#define FW_CFG_PORT_DATA 0x0511
#define FW_CFG_DMA_ADDR_HIGH 0x0514
#define FW_CFG_DMA_ADDR_LOW 0x0518
#endif
static int fw_cfg_detected;
static uint8_t fw_ver;
@ -43,10 +50,14 @@ static int fw_cfg_present(void)
static void fw_cfg_select(uint16_t entry)
{
if (fw_ver & FW_CFG_VERSION_DMA)
if (fw_ver & FW_CFG_VERSION_DMA) {
fw_cfg_dma(FW_CFG_DMA_CTL_SELECT | entry << 16, NULL, 0);
else
outw(entry, FW_CFG_PORT_CTL);
} else {
#ifdef __ARCH_GENERIC_IO_H__
entry = cpu_to_be16 (entry); // Big endian if MMIO
#endif
outw(entry, FW_CFG_PORT_CTL); // Little endian if IO-port
}
}
static void fw_cfg_read(void *dst, int dstlen)