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mb/google/ocelot/var/ojal: Add initial GPIOs config

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Configure GPIOs according to schematics revision 0.9.
RDC kit no:840138

BUG=b:437459757
TEST=Build ojal board

Change-Id: I95c2f84c19b00847ce7fb11d62477b4920ad90ec
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89126
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varun Upadhyay 2025-09-10 00:48:32 +05:30 • committed by Matt DeVillier
commit 82a9e601bd
1 changed files with 94 additions and 110 deletions
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204
src/mainboard/google/ocelot/variants/ojal/gpio.c
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@ -31,18 +31,18 @@ static const struct pad_config gpio_table[] = {
/* GPP_A08: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
/* GPP_A10: WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_A10, 1, PLTRST),
/* GPP_A11: WLAN_RST_N */
PAD_CFG_GPO(GPP_A11, 1, PLTRST),
/* GPP_A12: WIFI_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
/* GPP_A13: PCIE_LNK_DOWN */
PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
/* GPP_A15: CODEC_GPIO_EN */
PAD_CFG_GPO(GPP_A15, 1, DEEP),
/* GPP_A09: NC */
PAD_NC(GPP_A09, NONE),
/* GPP_A10: NC */
PAD_NC(GPP_A10, NONE),
/* GPP_A11: NC */
PAD_NC(GPP_A11, NONE),
/* GPP_A12: NC */
PAD_NC(GPP_A12, NONE),
/* GPP_A13: TCH_PAD_INT_N */
PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT),
/* GPP_A15: NC */
PAD_NC(GPP_A15, NONE),
/* GPP_B */
/* GPP_B00: USBC_SML_CLK_PD */
@ -57,7 +57,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B04, NONE),
/* GPP_B06: SOC_PDB_CTRL */
PAD_CFG_GPO(GPP_B06, 0, DEEP),
/* GPP_B08: ISH_GP_4_SNSR_HDR */
/* GPP_B08: NC */
PAD_NC(GPP_B08, NONE),
/* GPP_B09: BT_RF_KILL_N */
PAD_CFG_GPO(GPP_B09, 1, DEEP),
@ -69,14 +69,16 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B14: GPP_B14_DDSP_HPDB */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
/* GPP_B16: COINLESS_MODE_SELECT */
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
/* GPP_B16: NC */
PAD_NC(GPP_B16, NONE),
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_B20: WWAN_RST_N */
/* GPP_B20: SOC_KB_MATRIX */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B22: SOC_CAM_WP */
PAD_CFG_GPO(GPP_B22, 0, DEEP),
/* GPP_B24: ESPI_ALERT0_EC_R_N */
PAD_NC(GPP_B24, NONE),
/* GPP_B25: None */
@ -101,18 +103,18 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C07, NONE),
/* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */
PAD_CFG_GPO(GPP_C08, 1, PLTRST),
/* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
/* GPP_C09: NC */
PAD_NC(GPP_C09, NONE),
/* GPP_C10: WIFI_RF_KILL_N */
PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
/* GPP_C11: NC */
PAD_NC(GPP_C11, NONE),
/* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
/* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
/* GPP_C13: NC */
PAD_NC(GPP_C13, NONE),
/* GPP_C14: NC */
PAD_NC(GPP_C14, NONE),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
/* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */
@ -129,30 +131,30 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
/* GPP_D */
/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
PAD_CFG_GPO(GPP_D01, 1, DEEP),
/* GPP_D01: NC */
PAD_NC(GPP_D01, NONE),
/* GPP_D02: SOC_WP_OD */
PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_D03: X4_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
/* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */
/* GPP_D03: NC */
PAD_NC(GPP_D03, NONE),
/* GPP_D07: NC */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */
/* GPP_D08: NC */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: I2S_MCLK_HDR */
PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
/* GPP_D10: HDA_BCLK (HDR) */
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
/* GPP_D11: HDA_SYNC (HDR) */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
/* GPP_D12: HDA_SDO (HDR) */
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
/* GPP_D13: HDA_SDI0 (HDR) */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* GPP_D16: HDA_RST_N (HDR) */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
/* GPP_D17: HDA_SDI1 (HDR) */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* GPP_D09: NC */
PAD_NC(GPP_D09, NONE),
/* GPP_D10: NC */
PAD_NC(GPP_D10, NONE),
/* GPP_D11: NC */
PAD_NC(GPP_D11, NONE),
/* GPP_D12: NONE */
PAD_NC(GPP_D12, NONE),
/* GPP_D13: NC */
PAD_NC(GPP_D13, NONE),
/* GPP_D16: NC */
PAD_NC(GPP_D16, NONE),
/* GPP_D17: NC */
PAD_NC(GPP_D17, NONE),
/* GPP_D19: NC */
PAD_NC(GPP_D19, NONE),
/* GPP_D21: GPP_D21_UFS_REFCLK_R */
@ -161,36 +163,36 @@ static const struct pad_config gpio_table[] = {
/* GPP_E */
/* GPP_E01: PM_SLP_DRAM_N */
PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
/* GPP_E02: NC */
/* GPP_E02: VR_ALERT#_R */
PAD_NC(GPP_E02, NONE),
/* GPP_E03: X4_DT_PCIE_RST_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E05: GPP_E5_FPS_PWREN */
PAD_CFG_GPO(GPP_E05, 1, DEEP),
/* GPP_E06: GPP_E6_PEN_DETECT */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
/* GPP_E07: LAN_GPIO_RST_N */
PAD_CFG_GPO(GPP_E07, 1, PLTRST),
/* GPP_E08: EC_SOC_INT_ODL */
PAD_CFG_GPI(GPP_E08, NONE, DEEP),
/* GPP_E03: NC */
PAD_NC(GPP_E03, NONE),
/* GPP_E05: NC */
PAD_NC(GPP_E05, NONE),
/* GPP_E06: CAM_PRIVACY */
PAD_CFG_GPO(GPP_E06, 1, DEEP),
/* GPP_E07: NC */
PAD_NC(GPP_E07, NONE),
/* GPP_E08: NC */
PAD_NC(GPP_E08, NONE),
/* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
/* GPP_E10: M2_UFS_DET_SEL_N */
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
/* GPP_E10: NONE */
PAD_NC(GPP_E10, NONE),
/* GPP_E11: NC */
PAD_NC(GPP_E11, NONE),
/* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
/* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
/* GPP_E14: NC */
PAD_NC(GPP_E14, NONE),
/* GPP_E15: NC */
PAD_NC(GPP_E15, NONE),
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
/* GPP_E17: GPP_E17_GSPI0A_CS0 */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
/* GPP_E17: NC */
PAD_NC(GPP_E17, NONE),
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
/* GPP_E19: FPS_INT_N */
@ -215,18 +217,18 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
/* GPP_F05: CRF_CLKREQ_R */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
/* GPP_F06: DISC_WLAN_WWAN_COEX3 */
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
/* GPP_F07: FUSA_DIAGTEST_EN_HDR */
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
/* GPP_F06: NC */
PAD_NC(GPP_F06, NONE),
/* GPP_F07: NC */
PAD_NC(GPP_F07, NONE),
/* GPP_F08: TCH_PNL1_PWR_EN */
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
/* GPP_F09: M2_UFS_RST_N */
PAD_CFG_GPO(GPP_F09, 1, DEEP),
/* GPP_F10: X4_PCIE_SLOT1_PWR_EN */
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
/* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
/* GPP_F10: SOC_EC_INT */
PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F11: NC */
PAD_NC(GPP_F11, NONE),
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
@ -237,10 +239,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16: GPP_F16_GSPI0A_CLK */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F17: CODEC_IRQ_HDR */
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
/* GPP_F18: TCH_PAD_INT_N */
PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
/* GPP_F17: NC */
PAD_NC(GPP_F17, NONE),
/* GPP_F18: GPP_F18_GSPI0A_CS0 */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
/* GPP_F19: NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: CSE_EARLY_SW */
@ -257,10 +259,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
/* GPP_H03: MIC MUTE */
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
/* GPP_H04: CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
/* GPP_H05: CNV_MFUART2_TXD */
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
/* GPP_H04: NC */
PAD_NC(GPP_H04, NONE),
/* GPP_H05: NC */
PAD_NC(GPP_H05, NONE),
/* GPP_H06: I2C3_SCL_AUDIO_HDR */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SDA_AUDIO_HDR */
@ -269,10 +271,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10: UART0_BUF_RTS */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
/* GPP_H11: UART0_BUF_CTS */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
/* GPP_H10: NC */
PAD_NC(GPP_H10, NONE),
/* GPP_H11: NC */
PAD_NC(GPP_H11, NONE),
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
@ -291,28 +293,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_TTK_CHROME */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* GPP_H23: TP */
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
/* GPP_H24: TP */
PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
/* GPP_S */
/* GPP_S00: SNDW3_CLK_CODEC (HDR) */
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
/* GPP_S01: SNDW3_DATA0_CODEC (HDR) */
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
/* GPP_S02: SNDW3_DATA1_CODEC (HDR) */
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
/* GPP_S03: SNDW3_DATA2_CODEC (HDR) */
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
/* GPP_S04: DMIC0_CLK (HDR) */
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
/* GPP_S05: DMIC0_DATA (HDR) */
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
/* GPP_S06: DMIC1_CLK (HDR) */
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
/* GPP_S07: DMIC1_DATA (HDR) */
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
/* GPP_H23: NC */
PAD_NC(GPP_H23, NONE),
/* GPP_H24: NC */
PAD_NC(GPP_H24, NONE),
/* GPP_V */
/* GPP_V00: PM_BATLOW_N */
@ -322,7 +306,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_V02: LANWAKE_N_R */
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
/* GPP_V03: PWRBTN_MCP_N */
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
/* GPP_V04: PM_SLP_S3_N */
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
/* GPP_V05: PM_SLP_S4_N */
@ -335,8 +319,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
/* GPP_V09: PM_SLP_S5_N */
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
/* GPP_V10: LANPHYPC_R_N */
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
/* GPP_V10: NC */
PAD_NC(GPP_V10, NONE),
/* GPP_V11: PM_SLP_LAN_N */
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
/* GPP_V12: WAKE_N */