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sb/intel/lynxpoint: Enable PCIe Relaxed Order

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Follow Lynx Point PCH reference code version 1.9.1 to enable PCIe
Relaxed Order.

Change-Id: If7ba4e826adfc8c220ecc68c4a456fbe3cb99667
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57504
Reviewed-by: Lean Sheng Tan <tanleansheng@outlook.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
This commit is contained in:
Angel Pons 2021-09-08 15:39:35 +02:00 • committed by Matt DeVillier
commit 67e3579d61
2 changed files with 14 additions and 0 deletions
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9
src/southbridge/intel/lynxpoint/lpc.c
View file

@ -272,6 +272,15 @@ static void pch_power_options(struct device *dev)
reg16 = RCBA16(0x3f02);
reg16 &= ~0xf;
RCBA16(0x3f02) = reg16;
/* Enable PCIe Relaxed Order */
reg32 = RCBA32(0x2314);
reg32 |= 1 << 31 | 1 << 7;
RCBA32(0x2314) = reg32;
reg16 = RCBA16(0x1114);
reg16 |= 1 << 15 | 1 << 14;
RCBA16(0x1114) = reg16;
}
static void configure_dmi_pm(struct device *dev)

5
src/southbridge/intel/lynxpoint/pcie.c
View file

@ -685,8 +685,13 @@ static void pch_pcie_early(struct device *dev)
pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
else
pci_update_config32(dev, 0x200, ~0xfffff, 0);
pci_update_config32(dev, 0x320, ~(3 << 20 | 7 << 6), 1 << 20 | 3 << 6);
}
/* Enable PCIe Relaxed Order. */
pci_or_config32(dev, 0x320, 3 << 23);
/* Read and write back write-once capability registers. */
pci_update_config32(dev, 0x34, ~0, 0);
pci_update_config32(dev, 0x40, ~0, 0);