mb/asus/p8z77-m_pro: Enable serial port A instead

Boardview shows the COM port header is connected to serial port A on the
super I/O chip while serial port B pins are unconnected, but it has been
coded for serial port B which cannot be correct.
Change to initialize serial port A instead.

This aligns it with other variants in the family, allowing it
to take advantage of future bootblock code unification.

Change-Id: I8c1a46bef7d9c89f423f8fea9a826b9549d783b4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/asus/p8x7x-series/Kconfig

@@ -33,6 +33,7 @@ config BOARD_ASUS_P8Z77_M_PRO
 	select DRIVERS_ASMEDIA_ASM1061 # for ASM1061 eSATA
 	select MEMORY_MAPPED_TPM
 	select SUPERIO_NUVOTON_NCT6779D
+	select SUPERIO_NUVOTON_COMMON_COM_A
 
 config BOARD_ASUS_P8Z77_V_LX2
 	select BOARD_ASUS_P8X7X_SERIES

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c

@@ -11,7 +11,7 @@
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/pei_data.h>
 
-#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP2)
+#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
 
 void bootblock_mainboard_early_init(void)
 {

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb

@@ -33,10 +33,10 @@ chip northbridge/intel/sandybridge
 			device ref lpc on
 				chip superio/nuvoton/nct6779d
 					device pnp 2e.1 off end	# Parallel
-					device pnp 2e.2 off end	# UART A
-					device pnp 2e.3 on	# UART B, IR
-						io 0x60 = 0x2f8		# COM2 address
+					device pnp 2e.2 on	# UART A
+						io 0x60 = 0x3f8
 					end
+					device pnp 2e.3 off end	# UART B, IR
 					device pnp 2e.5 on	# PS2 KBC
 						io  0x60 = 0x0060	# KBC1 base
 						io  0x62 = 0x0064	# KBC2 base