soc/amd/common/block/psp: Add comments
Explain when the MBOX_PSP return codes are send and which behaviour is invoked by the PSP when seeing such return codes. Change-Id: Ibe7ceb5d7cd025f3b3ab0c9167d23f6eb664c165 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88511 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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2 changed files with 24 additions and 4 deletions
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@ -143,10 +143,22 @@ enum mbox_p2c_status {
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MBOX_PSP_SUCCESS = 0x00,
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MBOX_PSP_INVALID_PARAMETER = 0x01,
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MBOX_PSP_CRC_ERROR = 0x02,
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MBOX_PSP_COMMAND_PROCESS_ERROR = 0x04,
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MBOX_PSP_UNSUPPORTED = 0x08,
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MBOX_PSP_SPI_BUSY_ASYNC = 0x0a,
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MBOX_PSP_SPI_BUSY = 0x0b,
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/*
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* Send to PSP when the requested SPI command in the psp_smi_handler()
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* handler failed due to an unknown error. The PSP usually doesn't like
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* seeing this return code and will stop operating.
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*/
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MBOX_PSP_COMMAND_PROCESS_ERROR = 0x04,
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MBOX_PSP_UNSUPPORTED = 0x08,
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MBOX_PSP_SPI_BUSY_ASYNC = 0x0a,
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/*
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* Send to PSP when the requested SPI command in the psp_smi_handler()
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* handler cannot be executed right away. This can happen when the SPI
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* flash is busy or the SPI controller is busy or being used by ring 0.
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*
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* The PSP will raise an SMI later again.
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*/
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MBOX_PSP_SPI_BUSY = 0x0b,
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};
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uintptr_t get_psp_mmio_base(void);
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@ -92,6 +92,14 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_
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return MBOX_PSP_SUCCESS;
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}
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/*
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* Returns true when the SPI flash is busy, the SPI controller is busy or the SPI
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* MMIO register access is blocked by ring0. When the SPI flash is busy all
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* operations, including reading, would fail.
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* Thus even memory mapped structures like FMAP would not be accessible
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* from memory mapped SPI flash (ROM2/ROM3). Caller must return MBOX_PSP_SPI_BUSY
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* to PSP when this function returns true.
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*/
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static bool spi_controller_busy(void)
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{
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bool busy;
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