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mb/google/ocelot: Update wake event mapping for gspi0

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This change corrects the ACPI wake event mapping for the gspi0 device,
ensuring the wake signal is routed through GPE0_DW2_19 instead of
GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in
devicetree.cb

Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Sowmya Aralguppe 2025-09-22 11:18:21 +05:30 • committed by Matt DeVillier
commit 36d2dc7cb9
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
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@ -541,7 +541,7 @@ chip soc/intel/pantherlake
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)"
register "wake" = "GPE0_DW1_19"
register "wake" = "GPE0_DW2_19"
register "has_power_resource" = "true"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"