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mb/google/ocelot/var/ocelot: Update USB and TCSS port configuration

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The list of changes are as follows
1. Modified USB2 port 7 from M.2 WLAN to discrete Bluetooth device.
2. Updated both Type-C ports to OC_SKIP to reflect virtual ports.
3. Adjusted Type-C port ACPI group assignments for USB3 ports.
4. Reduced display device count from 5 to 4 by removing DD04.
5. Updated comments and port usage to clarify Type-A and Type-C port
   assignments.

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I1e8cc92463a462c9baa78cd6d79637004340f7e2
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Sowmya Aralguppe 2025-08-04 11:55:56 +05:30 • committed by Matt DeVillier
commit 59bd0e3206
2 changed files with 7 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
View file

@ -28,8 +28,6 @@ chip soc/intel/pantherlake
register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
# Enable SAGv
register "sagv" = "SAGV_ENABLED"

18
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
View file

@ -69,14 +69,13 @@ chip soc/intel/pantherlake
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # FPS
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # M.2 WLAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2 (redriver topology)
#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # TCSS Module - Type-A over TCP module
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 (Virtual OC)
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 2 (Virtual OC)
register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
@ -129,7 +128,7 @@ chip soc/intel/pantherlake
probe DISPLAY DISPLAY_TOUCH_PRESENT
probe DISPLAY DISPLAY_NO_TOUCH_PRESENT
chip drivers/gfx/generic
register "device_count" = "5"
register "device_count" = "4"
# DDIA for eDP
register "device[0].name" = ""LCD0""
register "device[0].type" = "panel"
@ -144,10 +143,7 @@ chip soc/intel/pantherlake
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
device generic 0 on end
end
end
@ -351,13 +347,13 @@ chip soc/intel/pantherlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(4, 2)"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref tcss_usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 2)"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref tcss_usb3_port1 on end
end
end