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mb/google/fatcat/var/lapis: Update thermal strategy

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According to the schematic diagram, lapis is designed
with five temperature detection nodes, so the initial
thermal strategy was updated.

BUG=b:438785495
TEST=emerge-fatcat coreboot

Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Hualin Wei 2025-09-22 20:21:23 +08:00 • committed by Matt DeVillier
commit 3a33217349
1 changed files with 23 additions and 8 deletions
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31
src/mainboard/google/fatcat/variants/lapis/overridetree.cb
View file

@ -65,10 +65,11 @@ chip soc/intel/pantherlake
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DDR_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""wwan""
register "options.tsr[0].desc" = ""VR""
register "options.tsr[1].desc" = ""DDR""
register "options.tsr[2].desc" = ""Top""
register "options.tsr[3].desc" = ""SSD""
register "options.tsr[4].desc" = ""Charger""
## Active Policy
# FIXME: below values are initial reference values only
@ -108,6 +109,18 @@ chip soc/intel/pantherlake
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(60, 60),
TEMP_PCT(55, 50),
TEMP_PCT(50, 40),
TEMP_PCT(45, 30),
}
},
[4] = {
.target = DPTF_TEMP_SENSOR_4,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
@ -128,16 +141,18 @@ chip soc/intel/pantherlake
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
[5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 80, 5000),
}"
## Critical Policy
# TODO: below values are initial reference values only
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 91, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 91, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 91, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 91, SHUTDOWN),
[5] = DPTF_CRITICAL(TEMP_SENSOR_4, 91, SHUTDOWN),
}"
## Power Limits Control