Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.
It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.
Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.
TEST=Lenovo X220 still boots.
Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the same wakeup method that Meteor Lake uses to Panther Lake.
TEST=Able to build and boot google/moonstone where able to wake
the device using differnt USB devices like USB FP, KB and Mouse.
Change-Id: Id680b443791c3dbc502d1b6776fd0fa03bd80691
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit adds a wake configuration to the cnvi_bluetooth device for
the ruby variant. The "wake" setting is now registered to "GPE0_PME_B0"
using the common CNVi block. This enhancement ensures that the
cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: If1b3af2a9ad8c3e3800f5c839190727d78122853
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
When disabling slow battery charging, explicitly set the Fast Charge
Current (FCC) configuration to 0x8c (disable) for both SMB1 and SMB2
controllers.
This ensures that the PMIC charging registers are returned to a
neutral/safe state while disabling the charging.
BUG=b:481546101
TEST=Build and boot Bluey. Verified that SMB1/SMB2_CHGR_MAX_FCC_CFG
registers are cleared during the disable_slow_battery_charging call.
Change-Id: Ic5da492b097747dec88b117ac021759644b8b816
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91121
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the juchi variant of the jubilant project by
copying the files to a new directory named for the variant.
BUG=b:481602501
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUCHI.
Change-Id: I4a1919f6a2480e4e2f993fa24658836a1739714c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Remove the sa_get_tseg_size() function and replace all its usage with
CONFIG_SMM_TSEG_SIZE configuration option. The TSEG size is now
obtained directly from the configuration instead of being calculated
dynamically. The existing calculation assumes GSM and TSEG regions are
contiguous, but there is no guarantee this is always true depending on
how FSP operates. This could lead to incorrect size calculations.
Using CONFIG_SMM_TSEG_SIZE is more reliable as this value is provided
to the FSP during initialization.
This change:
- Removes sa_get_tseg_size() function declaration and implementation
- Updates smm_region() to use CONFIG_SMM_TSEG_SIZE directly
- Updates Alder Lake, Meteor Lake, and Panther Lake system agent code
to use CONFIG_SMM_TSEG_SIZE instead of sa_get_tseg_size()
Before (sa_get_tseg_size):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] sa_get_tseg_size:0x3c00000
[DEBUG] New SMBASE=0x7b5ec000 IEDBASE=0x7b800000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfc400c00
System hangs during SMM relocation
After (CONFIG_SMM_TSEG_SIZE):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] CONFIG_SMM_TSEG_SIZE:0x2000000
[DEBUG] New SMBASE=0x799ec000 IEDBASE=0x79c00000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfe000c00
[DEBUG] Relocation complete.
System boots successfully
BUG=none
Change-Id: Ie2a1f3dd68941924e056a12f01857c1182b69198
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91063
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update fast_vmode_i_trip array references as per 813278_Rev2p1p1 to use
PTL_SKU_* constants instead of PTL_CORE_* constants. This aligns with
the corrected indexing scheme used in the SoC VR configuration code.
TEST=Verify IccLimit value for different SKUs in FSP debug log
Change-Id: I90a5c6e03633ba2b4a0a132ed9f94d8e5c4ff8bf
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91049
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Introduce the infrastructure required to display an off-mode charging
notification. This is used when a device boots due to power cable
insertion but should remain in a charging state rather than booting
the full operating system.
Changes:
- Add BOOTSPLASH_OFF_MODE_CHARGING to bootsplash_type.
- Define platform_is_off_mode_charging_active() with a weak inline
fallback to allow platforms to signal off-mode charging status.
- Update bmp_logo.c to recognize "off_mode_charging.bmp" and select
it as the active logo type when charging is active.
- Modify render_bmp.c to handle layout and rendering for the charging
logo, including support for footer text if enabled.
- Ensure the rendering flow bails out early after displaying the
charging notification to prevent standard OS boot splash.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ief4c65eaf0178ff3d736363c3e56acfe1adba14a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR to support
rendering a dedicated splash screen when a device is in an off-mode
charging state. This provides visual feedback to the user when a
device autoboots upon power cable insertion instead of performing
a full OS boot.
Changes:
- Add Kconfig options for enabling the indicator and specifying
the logo path.
- Update Makefile.mk to include the off-mode charging BMP file
in CBFS when the feature is enabled.
- Depend on BMP_LOGO infrastructure for asset rendering.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ib09de15ca3526bf5b10f7404dc58032d63c01e6d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit increases the default pre-allocated IGD stolen memory size
from 64MB to 128MB in FSP-M parameters. This ensures sufficient memory
is allocated for higher resolution displays and graphics-intensive
early-boot tasks on Panther Lake platforms.
BUG=b:481209815
TEST=Able to build and boot google/ruby.
Change-Id: Idd3f1bcb9cbb27adc18a31c0dd5952e901ecf5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the Integrated Graphics Device (IGD) stolen memory size enum
values to align with the Panther Lake Reference Code. This change
introduces the 96MB definition and corrects the value for 128MB.
Modified values:
- IGD_SM_96MB: Added as 0x03
- IGD_SM_128MB: Updated from 0x03 to 0x04
Change-Id: Id7a547e8a530294a76f201e87865e8508ff67a92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91140
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ancient microcode update files do not have a total_size field.
Add support for such platforms and return 2048 in that case.
Change-Id: I952edc12cccf24f396d940bc594d8ef97826a253
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90910
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set CBFS_SIZE to match the SI_BIOS region size defined in each board's
chromeos.fmd file, up to a maximum of 16MiB. This ensures the largest
possible region is available for CBFS use without requiring manual
CBFS_SIZE overrides. The size is capped at 16MiB as that is the
largest area that can be memory mapped, the FIT pointer must be
located in the top 16MiB.
This change applies to all Intel-based Google mainboards with ChromeOS
FMD layouts that explicitly define SI_BIOS region sizes, and which do
not define a default non-ChromeOS FMAP layout (octopus, reef).
For boards with multiple ChromeOS FMD files, CBFS_SIZE is set
conditionally based on ROM size or silicon variant, using the
same logic as to select the ChromeOS FMD file.
This eliminates the need to override CBFS_SIZE when using larger
payloads (e.g., edk2) or multiple payloads, making the default
configuration more flexible.
TEST=build/boot various google boards with edk2 payload without
overriding CBFS_SIZE.
Change-Id: If7ef6cc96afcdd025958c578ad80fd0db641582a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This solves the remark:
```
dsdt.asl 28: Name (RBUF, ResourceTemplate ()
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.PERC._CRS)
```
Change-Id: Ifff2678e351cf6d92a7fba5d3cf64413e15393c0
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On these two mainboards, a Gen1 device is connected on PCIe RP #7.
Measurements have shown that a value of -0.137 dB yields an optimal eye
TX mask test.
BUG=none
TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope
Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides support for board-specific fine-tuning of PCIe root
ports.
The following parameters can be adjusted.
PchPcieHsioTxGen1DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 1
PCIe devices
PchPcieHsioTxGen2DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 2
PCIe devices
PchPcieHsioTxGen3DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 3
PCIe devices
PchPcieHsioTxGen1DeEmph:
- Adjust or fine-tune the amount for PCIe Gen 1 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph3p5:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph6p0:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -6.0dB mode
Change-Id: I7b51de2b7f75e15d902e471a19b8b29166ddfb48
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Change the HID used from OVTIDB10 to OVTI13B1 for proper attachment
under Windows. Linux/ChromeOS don't use the HID, and so are unaffected
by the change.
TEST=build/boot Win11 on Teliks, verify MIPI camera driver loads
properly.
Change-Id: Ia81bd8cfaf6bb160f4f18214edccdf425d22cf6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91108
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the corresponding sensor_name value used by the Windows drivers for
each camera sensor. Update the name used for Redrix based on testing.
This value is not used by ChromeOS/Linux.
TEST=build/boot Win11 on redrix, magolor. Verify IPU/MIPI camera works
properly using available drivers.
Change-Id: Id4fba3667f9497f71787e504bf244d54e433e552
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Adjust the option groups into more logical groups, and ensure all
are alphabetised.
Change-Id: I8bac31206e16146ce55c3946fa8e8e4accdc7060
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The descriptor was updated to support Raptor Lake upgrades, which
increased the ME region size.
Change-Id: I0fa909e8aa58c8825fb9cd0301e9bbc60cf1ca89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached.
This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer
writes.
Ensure BAR ranges get a cacheable attribute instead of falling back to
UC.
Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the local LOW_BATTERY_SHUTDOWN_DELAY_SEC macro with the newly
introduced, globally configurable PLATFORM_POST_RENDER_DELAY_SEC
Kconfig.
This aligns the bluey mainboard with the shared platform delay logic,
ensuring a consistent user experience across products while allowing
easier adjustment of the shutdown/teardown timing buffer.
TEST=Verified build and boot on bluey; critical battery shutdown still
respects the intended 5-second delay (as per default Kconfig).
Change-Id: I1ddab276e797b793974e0205a91ba832f3085ead
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The existing PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC was strictly
tied to the low-battery indicator logic. This change renames and
generalizes the configuration to PLATFORM_POST_RENDER_DELAY_SEC.
By moving this out of the low-battery specific conditional block in
Kconfig, the delay can now be utilized more broadly. While it still
ensures the low-battery warning remains visible before power-off, it
can now also be used to ensure display synchronization or user
notifications are visible before passing control to the OS in normal
boot flows.
Updated Intel common reset logic to utilize the renamed config.
BUG=b:473480933
TEST=Verified that low-battery shutdown still respects the 5-second
default delay on target hardware.
Change-Id: I0277ea278fb299499f6eab2be983761a8f6ba536
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91104
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'const' qualifier is unnecessary for the return values of the
following:
- list_next()
- list_prev()
- list_first()
- list_last()
Therefore, drop it. No caller needs to be changed.
Change-Id: I0f5bc2b0ed3cd47d0d6355c8dffea17f6e085407
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91113
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Support for the rex touchscreen panel was needed for the RVP to validate touchscreen functionality. The LPSS touchscreen is mapped to I2C bus 4 and the rex panel is mapped to address 0x10.
BUG=b:458429110
TEST=None
Change-Id: I99b2c7beaab63da1877995c655ff8eddf9c3a69f
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.
No functional change, thus untested.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.
Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME
Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras
Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).
For more information please refer to #854345 (Intel CNDA).
Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree.
BUG=b:481143310
TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design.
Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The Matsu hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=443612246
TEST=Build and boot to OS on Matsu, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I84db81c17afffafbdb6c7abcc752009c824bc2ed
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91086
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The Kinmen hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=460038237
TEST=Build and boot to OS on Kinmen, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I5e20c247bd45427f817e7afd8355a71c7a9c161c
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for BWMYAX32P8A-32G
DRAM Part Name ID to assign
BWMYAX32P8A-32G 3 (0011)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I4b26b3c74c2985d9b663bc8eb72824d1ca82850b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91052
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Update SaGv work point 4 frequency value as per recommendation
from power and performance team.
BUG=b:461762075
TEST=Boot to OS on fatcat board, verified performance improvements
and frequency setting.
Change-Id: Ic4dfe6bf5a441b491a27e952010a43d4f7a68af5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).
Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.
TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load microcode from CBFS before setting up MTRRs using
x86_setup_mtrrs_with_detect(), since it will remove caching the
SPI flash MMIO area and thus slow down CBFS accesses.
TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system
boots 6msec faster than before.
Change-Id: I3fafb98c1348daa549448707db88954316a12ff2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change introduces a check to ensure Power Delivery (PD)
negotiation is enabled when the device is in a specific vboot state.
PD negotiation will now be enabled if:
1. It is explicitly required by the hardware sync logic.
2. The device is in Developer Mode.
3. The device is in Recovery Mode.
4. A recovery request is pending.
This ensures that charging and PD sync are prioritized during
critical recovery and development paths.
This patch ensures the factory process remains powered by enabling
early charging based on the specific vboot mode.
In normal user scenarios, early charging is bypassed to allow higher
-level software to manage power negotiation according to standard
policy.
BUG=b:481546101
TEST=Build and boot on google/quartz. Verified PD negotiation is
active in developer/recovery mode.
Change-Id: I44b2ebd4fe3eec78a6df235df6282264dd97341f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91096
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The current bmp_logo_filename implementation returns static filenames
based on Kconfig or ChromeOS branding levels. This lacks flexibility
for boards that need to select a logo dynamically at runtime (e.g.,
based on SKU ID or hardware straps).
Introduce a weak function mainboard_bmp_logo_filename() that can be
overridden by mainboard code. If the mainboard implementation returns
a non-NULL string, that filename is used; otherwise, the logic falls
back to the existing default behavior.
BUG=None
BRANCH=None
TEST=Verified that a mainboard can override the logo filename by
implementing mainboard_bmp_logo_filename. Verified default behavior
is preserved when no override is present.
Change-Id: Ia410dfb2a7a88779bb8eb4551605747bb326d353
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91082
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
waddledee dosn't have a MIPI camera, so drop the unused ipu devicetree
reference.
Change-Id: Ieca23f03d83fe1feeb026a923aec2c5fab6a9fe5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
- Add IPUA device under igpu (gfx/generic) for variants with IPU:
bugzzy, drawcia, haboki, lalala, magolor, storo, waddledoo
- Set ssdb.link_used to match cio2_prt
- Drop ssdb.rom_type and rom_address from mipi_camera sensor nodes;
JSL doesn't use this, and it causes a BSOD under Windows
- Add missing sensor_name for CAMERA_SENSOR on magolor and waddledoo
TEST=build/boot Win11 on magolor, verify MIPI camera functional
Change-Id: I7fca3c6bb8bca9271a4dbaf888cc28304d6545a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91066
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For dedede laptops, switch from using GMA_DEFAULT_PANEL(0), previously
set in the baseboard, to using a per-variant gfx generic chip driver,
so that variants which use IPU/MIPI cameras can add the IPUA camera
device in a subsequent commit.
For dedede laptops, this is a no-op; for Chromeboxes, it removes the
previously defined internal panel which they do not have.
TEST=build/boot dexi, magolor variants. verify ACPI brightness controls
still functional under Linux and Windows for the latter.
Change-Id: I83fd2d952ca785bef8210024cbbb9280688d6a5e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
JSL was missing an entry for the IGD, preventing the use of
DRIVERS_GFX_GENERIC since the call to acpi_device_scope() for it
returned null. Add the missing IGD entry, consistent with other
modern Intel SoCs.
TEST=build/boot google/magolor with chip drivers/gfx/generic entry
and verify SSDT entry correctly created.
Change-Id: Idf1d8992b45c60f68fd2b156c6e7cae816df84b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
According to Intel SA Doc#873795, select HAVE_CHIPSETINIT_BINARY
on nissa and trulo baseboard.
BUG=b:447290550
TEST=1. build coreboot
2. check log to confirm load chipsetinit.bin successfully.
Change-Id: I66a0c1a3dbfbbf563461b319c5839910dfc11656
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90698
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kao, Ben <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gpio-keys is a Linux-specific ACPI interface, and the kernel driver
does not care what the status is. Windows does not have drivers
however, so set the ACPI status to HIDDEN to avoid an unknown device
from appearing in Device Manager.
TEST=build/boot Win11 on google/magolor, verify PENH device no longer
listed under Device Manager.
Change-Id: I8a476e57b36c26795bfe9605e725ba3d5f860b3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91068
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements the recommended BIOS power delivery settings
described in Intel WW03 2026 Wildcat Lake platform message of the
week (844458).
Key changes:
- Enable acoustic noise mitigation with SLEW_FAST_4 for GT domain
- Enable fast package C-state ramp disable for GT domain
- Update fast_vmode_i_trip to 25A (was 38A)
- Enable GT VR fast voltage mode and CEP
BUG=b:467349691
TEST=Build ocelot and verify that the system boots to UI with the
updated parameters.
[SPEW ] IccMax[1]:0x90
[SPEW ] EnableFastVmode[1]:0x1
[SPEW ] IccLimit[1]:0x64
[SPEW ] CepEnable[1]:0x1
[SPEW ] FastPkgCRampDisable[1]:0x1
[SPEW ] SlowSlewRate[1]:0x1
[SPEW ] AcousticNoiseMitigation:0x1
Change-Id: I76cefc79457c6bcfb250ba3525c501a126b526fb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Improving the driving capabilities of USB2 enables the eye
diagram of a USB camera to pass the test.
BUG=b:478790360
TEST=emerge-fatcat coreboot, EA test pass
Change-Id: Id400fb541fd1c797ea602e3f8e12be07ed05b5b8
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91047
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add TG-XTI05101 MIPI panel for Wugtrio.
Datasheet:TG-XTI05101-01A-SPEC-V1_20260202.pdf
BUG=b:479758139
TEST=emerge-staryu coreboot depthcharge libpayload chromeos-bootimage
can see the fw screen,jump to kernel and can see chromeos logo
BRANCH=corsola
Change-Id: Ibec69165fe39675d6e6ef4e0db7733825af7bf56
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90873
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use I2C block read command to access the VPD EEPROM to speed up
SMBIOS table generation, but keep the single byte read as fallback.
Shrink the size of the mainboard version string to not crossing the
128 byte block boundary.
TEST=On Lenovo X220 the BS_WRITE_TABLES is 15 msec faster.
Change-Id: Ida21a8dc653551440e79b062abcce9194d11bef4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
