- Convert the pch early chipset init code to reg_script format.
- Remove the generic romstage code from pch_early_init() as this
is now done in romstage_main().
- Use base addresses from broadwell/iomap.h
- Start the HPET counter after enabling it as it is needed by
the memory training reference code.
- Set PCH interrupt routing here instead of in mainboard code.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I66a8b54ec81d5126cf4d59196e0e06ea949286d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Move the System Agent initialization code to a reg_script
implementation and call that initscript in systemagent_early_init.
- Remove the function that was setting up graphics registers as
those are taken care of separately on a per-platform basis.
- Remove some workarounds from older chipsets that were touching
undefined registers in MCHBAR.
- Convert the base addresses to use broadwell/iomap.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I1235b631c120d55bf613cf2d195c40a5e5647cc2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to fill out the chipset_power_state structure for
use in romstage and determine the chipset previous sleep state.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic3d06d28071099f9b1d19ced7754f057cedce574
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This can be used to raise the core frequency to maximum, but
it may not take effect until BIOS_RESET_CPL bit has been set.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4841025bad4fa4ab61236e3d7f7f3172061ff39f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a significant change that is hard to break up. The basic
flow of the file comes from baytrail/romstage/romstage.c and was
overlayed on top of the existing haswell romstage_main and fixed
up where necessary.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I119c7033f4d2980f48e34ab413dfe4845491552b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199361
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Use PCH_DEV_LPC instead of special case for SMM code.
- Change RCBA macros to be SPIBAR macros
- Clean up include files
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I7d846e9c1c4627aea08fb09f2e85f86a98ec61a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
romstage: Move the smbus enable code into reg_script format and call
the script with the PCH_DEV_SMBUS device.
ramstage: Use appropriate headers.
both: Change use of old SMBUS_IO_BASE to SMBUS_BASE ADDRESS.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Icf8c70810f86fc56d0f595a80b6d70361f6f7cd8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to the romstage SPI code to read and return the
WPSR to determine the software write protect status at boot.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ia68c02317ed1c2149fd9de1f60598b6f101d9686
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the stack related helper functions to a separate file
at broadwell/romstage/stack.c.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I9a89899c505e5a99615dd0e4b46a3487e04089f2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EHCI debug structure was changed recently to be 36 bytes
instead of 24 bytes, this needs to be updated in the CAR setup
to use the proper size and also to avoid this region when setting
up the stack for romstage use.
Also fix a number of MTTR->MTRR typos and clean up some comments.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Icb0421f6bf11055cb26d7f26c0f0eb0265181b12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove special handling for PCH-LP since it is now the only
supported chipset type and rename azalia to hda.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ie0fac229165255b49554a59922a8228dc5efb1a6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199187
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This function will read the chipset register to determine the
interrupt assigned for SCI in order to create the ACPI MADT
IRQ override entry.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Idba2ab3d84fa843304d03b3e707c3678ed16e71e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199186
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use ACPI_BASE_ADDRESS instead of get_pmbase() throughout the file.
Remove special handling for old southbrige (non-LP) interface since
all supported chipsets for broadwell now use the new interface.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I729f23b68ed4ed916f06fb99545d8a2551212ef6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new file to contain the functions for finding the top of usable
memory. This is used in romstage (after raminit) and in ramstage.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I71cc010b4419c7b54820df04b5a80b2ad955905f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the basic pch_type/pch_revison functions and add
new ones for identifying WildcatPoint and WPT-ULX SKUs that
are used for special handling in driver code.
Add a new function to read a PCH soft strap which is also used
for special handling in driver code.
Remove stale chip_operations for the lynxpoint southbridge.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I00c3aa737f87561f16385cd986b024e226d93ccc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199183
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Only the "LP" variant interface to GPIOs is supported so drop
all the LP_ prefixes and remove the special handling for the
previous GPIO interface model.
Change all occurrences of get_gpiobase() to GPIO_BASE_ADDRESS.
Add a new function to initialize a single GPIO which can be used
by a mainboard to support specific setup and/or power sequence
requirements.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I8f645f914eb576e00b3c8feb93c8291d763640d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EHCI controller is disabled in refcode binary in the typical case,
it is only left enabled when using USBDEBUG. So the code to disable
the controller can be removed.
The XHCI controller clock gating setup is done in the ramstage
refcode binary so that code can be removed now. The SMM code for
preparing the controller prior to S3/S5 is reworked but still
made available to be called by the SMI handler.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I19d1df99d2ee5dbc9c93ca01b2d246432928d77f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide elog stub functions so eventlog support can be omitted
without littering code with "#if CONFIG_ELOG".
This makes it so coreboot can be built without eventlog support for
these platforms for debugging purposes.
BUG=none
BRANCH=none
TEST=compiled for Nyan and Rambi with CONFIG_ELOG unset
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibf56d29a09234068773378f99ad9bffd5480dc9c
Reviewed-on: https://chromium-review.googlesource.com/198647
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: I69b0a330acbff97ebb8dc3ce3e37f7452433b5dc
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197882
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2bd9b4250fe44c33a15f8615de4034cfff4cf3b5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Reviewed-on: https://chromium-review.googlesource.com/198324
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
The Eon SPI25 code had a number of issues:
- fix page write calculation
- fix erase segment
- fix id check
- fix sector size
- make commands EN25 generic
This make the code similar to other SPI25 devices used in coreboot.
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: Id83d94b7ae5ea1610804a943c657d95a29dc6247
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197881
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 090a8e4352890c43209bd17acc41281a3af89f16)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Conflicts:
src/drivers/spi/eon.c
Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Reviewed-on: https://chromium-review.googlesource.com/198323
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
- Use the PCI device ID macros for device addressing
- Use the IO map defines from broadwell/iomap.h
- Clean up some macro defines that were renamed
- Clean up comments
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I2c1e0bc397f6a58fb51406835a9aa37f1c049b0a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Use the CPUID defines to print CPU variant and stepping
information at boot.
- Use the LPC Device ID defines to print the PCH variant
at boot.
- Use the IGD Device ID defines to print the GT SKU at boot.
- Move report_memory_config() into romstage/report_platform.c
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I199abdf01ed570055a1933065a8e0d7f4799fcd8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add CPUIDs for haswell and broadwell for use in drivers
and for platform reporting.
- Add PCI Device IDs for the LPC and integrated graphics devices
for use in the drivers and for reporting the platform info.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I763d142d40f4883490b2777a6452b13e6262c5b3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198923
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Remove SMM interface to the management engine as it is no
longer used.
- Change the me_status() function to read PCI registers itself
instead of needing them passed in.
- Fix formatting issues in me_status.c including >80col
- Switch to using PCH_DEV_ME instead of PCH_ME_DEV
- Remove unused functions in me.c
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I2c382d47e1c5d80ddd77f71d342f8851ba12dbea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198922
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the name more generic since it applies to both haswell
and broadwell chips.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I46aa67e144deb79bd5348a4104da7dc0d0889329
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pull together all the used register definitions from the
cpu/northbridge/southbridge chip.h files into one structure
for the broadwell SOC.
Add a chip.c file that contains the main chip_operations
structure as well as a shared pci_operations structure that
can be used by other ramstage drivers.
The chip broadwell_enable function handles different bus types
and splits the work out to the right subsystem.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I42ceed278b3cd5c46c2384c3f6528246a2193cc8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These registers are in MCHBAR so they should live in the
system agent header instead of the CPU header.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I037e5b74943bca8e04fa65986c7e421f144da96a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a reset_system() function that is used in romstage and ramstage
code and a broadwell/reset.h header for it.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4f96f0506a1147382b46b3540ffd5f520894fdc5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the ACPI related defines and function prototypes to a new
header at broadwell/acpi.h.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Id3e3e92d535613e2a8ffbf6b39d07d1ac231e9bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the formatting throughout the ACPI code to be consistent
with the rest of the coreboot codebase
Also remove unused variables and clean up some comments
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I6fbd14f9faefa21cc4e17a6a509d00299c222fdd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198913
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the newly provided broadwell/iomap.h to get the base addresses
that need to be defined in ACPI.
Add device resource consumption ResourceTemplate() for these
base addresses.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I8dffd7e7d0722868c5477bc4b2b9d4621406a223
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the broadwell code only supports the "low power" variant
there is no need to check for it in the ACPI code.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I5347750cd627bcb4e4f5fce587df931725f417df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The GPIO controller device has been moved to separate gpio.asl
so remove the code from serialio.asl.
The SerialIO devices no longer have enable status reported in a
separate SSDT so remove the External defines.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: If06b609475dd2fc32a0333c9e38fc456c6116756
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The CTDP related methods are moved from systemagent.asl to a
new ctdp.asl file.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4d0df9af27501b925ec0f12daeb5980903a637d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Removed unused variables from the ACPI NVS region and separate
out the variables used to communicate SerialIO base address and
enable status.
Some now unused ACPI methods in globalnvs.asl have been removed.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I20e26c7ebfb25975f315c3e41e67fee3f50df539
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and
COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these
attributes are associated with each of the stages.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google boards. Image booted
successfully on link, rambi and nyan.
Change-Id: I10d36ff950712756fb16dcb4d315924d177846b5
Reviewed-on: https://chromium-review.googlesource.com/195574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others
from arch level Makefile.inc to top level Makefile.inc.
Also, organize Makefile.inc at arch level into per-stage rules and variables.
BUG=None
BRANCH=None
TEST=Compiled successfully. Image booted successfully on link,nyan and rambi.
Change-Id: I22f5ef692b740f84d73071534732286e809f3bc4
Reviewed-on: https://chromium-review.googlesource.com/195446
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google boards. Successfully booted
link image.
Change-Id: I42323ac33c236d26654a26b591378781aeecabd4
Reviewed-on: https://chromium-review.googlesource.com/195350
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Add the header file used to communicate information to the intel
reference code binaries. This is shared directly with the PEI
wrapper in the binary. A broadwell specific function is defined
to fill out platform specific information and a function prototype
is provided for the mainboard to implement.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ib3254cbd0c1a890ffb716cab551f68b6201812d2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This broadwell implementation will support Haswell ULT in
addition to broadwell CPUs. Add the latest available microcode
for the broadwell C0 and D0 parts as well as Haswell ULT.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198742
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Put some generic ramstage function prototypes into the a new
header at broadwell/ramstage.h for easy access. Some of these
functions are defined in a later commit.
This file also contains the exported 'broadwell_pci_ops' that can
be used by ramstage drivers and is defined in broadwell/chip.c
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Idfa1f9ab46d1bf4efbefea46548f97653786e6f1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198741
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Put all the exported romstage functions (that are not also defined
in ramstage) into broadwell/romstage.h for easy access.
Some of the stuff in this file is not used yet but will be part of
a later commit.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I69db33ba95afa3c3868c7c09ed53ed80567d17f4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
