Coolstar's Windows drivers require the IOM device to be visible to the
OS, so add a Kconfig to control this, which mainboards will select in
subsequent patches.
TEST=build/boot Win11 on rex/screebo, verify USB4 drivers functional.
Change-Id: I00ef9703179d87b7b476ef18d8d02fcafa9e14ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86792
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ] EnableTcssCovTypeA[0]= 0x00000000
[SPEW ] MappingPchXhciUsbA[0]= 0x00000000
[SPEW ] EnableTcssCovTypeA[1]= 0x00000001
[SPEW ] MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf
BUG=b:400809281
TEST=Able to build and boot google/Riven
Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly-created ACPI devices in common/acpi, to align with other
client SoCs.
Change-Id: Icc5da0b820101b3c651ed59a47aeab37440a6996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Iabd9dec2f6838c1dc4b1cad924ceb62c992f89c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
HEC1 and SRAM are defined in src/soc/intel/meteorlake/chipset.cb:
device pci 16.0 alias heci1 on end
device pci 14.2 alias pmc_shared_sram off end
Add entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors
in the kernel dmesg log, and add entries to soc_acpi_name() to ensure
that these names are returned during acpi_device_path() calls.
TEST=Build/boot Linux 6.x on screebo to confirm errors are not seen.
Change-Id: Id79054d2cb56daae238ac562b7b6c204926cdced
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86797
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The ACPI device path name handler for the fast SPI device is missing,
so add it to ensure that the names is returned from acpi_device_path()
calls.
TEST=Build/boot Win11 on screebo
Change-Id: Ibf5ab3bf6694875c357b999fe871a5b16f89ec62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These can be used by most/all client SoCs
Change-Id: I6622fa34f014bbe9fdd95a996332dfe5a07a92fb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.
Correct this by setting the scope of the IOM device to just _SB.
TEST=build/boot Win11 on google/drobit, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.
Change-Id: Ia089e723ccac5508cfaffc0204815b80bb209dd0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86819
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the IOM region is outside of the PCH MMIO address space, Windows
will report a device error for the IOM since the ACPI scope
is under PCI0, but the assigned resource range is not inside an
address range for any of PCI0's resources.
Correct this by setting the scope of the IOM device to just _SB.
TEST=build/boot Win11 on google/banshee, verify USB-C ports functional
and coolstar's IOM/TCSS drivers loaded without error.
Change-Id: I7e61341dd9b7548a079a1ce3b88025f6391f3203
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit a7a76b0dee ("soc/intel/meteorlake: Hook up FSP repo for IOT")
added logic to use the FSP repo for IOT boards, but in doing so
broke the automatic selection of FSP_USE_REPO when HAVE_INTEL_FSP_REPO
was selected. Fix this by removing the override for FSP_USE_REPO and
selecting HAVE_INTEL_FSP_REPO when FSP_TYPE_IOT is selected.
TEST=build/boot starlabs/starbook_mtl with IOT FSP binaries/headers
Change-Id: Iad946a23c569e27cafa35ce2e6fefd6be1d90666
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86845
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This reverts commit 491afc3cc7.
Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and
'PchPciePowerGating' UPDs are also available on ADL-N.
Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit rectifies a PIN mapping error in GPIO Community 3,
introduced by the removal of CPUJTAG PADs from the static ACPI entry.
CPUJTAG PADs are reserved for SoC debugging and should not be
configured by kernel drivers. To ensure accurate PIN mapping for
subsequent GPIO banks, this patch designates the CPUJTAG PAD range as
"RSVD" (Reserved) and exposes the corresponding GPIO PIN numbers. This
allows other GPIO banks within Community 3 to correctly adjust their
offsets.
Problem:
Prior to this fix, GPP_H0 was incorrectly assigned PIN 0 within GPIO
Community 3, deviating from the EDS.
Solution:
By marking the CPUJTAG range as RSVD, GPP_H0 is now correctly mapped
to PIN 15, aligning with the EDS definition.
Changes in details:
- Corrected the GPI3 to accurately calculate the GPIO PINs.
- Renamed CPUJTAG to RSVD (Reserved) and adjusted related definitions.
- Updated GPI3 device to reflect the RSVD group, including adding
subproperties and correcting group counts.
- Modified gpio_defs.h and gpio_soc_defs.h to reflect the RSVD name
change and pad count.
Change-Id: I9f32b54a8a0218cd993f01ccf5f0bb158877766a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86825
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the magic number 0x00000001 with the BIT(0) macro for
QCLIB_GA_ENABLE_UART_LOGGING. This improves readability and
maintainability by clearly indicating that a specific bit is being set.
TEST=Able to build google/herobrine.
Change-Id: Ie425a68c6721343ca53eb883d6278decca92bcad
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The MTL FSP headers in github do not include FirmwareVersionInfo.h, so
DISPLAY_FSP_VERSION_INFO_2 needs to be deselected when using FSP
binaries from the repo.
TEST=tested with subsequent patch
Change-Id: I53dae842f545b3d4fe34ded57916f33716777a7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refine dptx_get_edid function to read extension edid to bring up 2.8k
120hz OLED panel.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
EQ training pass
Change-Id: If35782950ae02d892ea697580fa4991595c21533
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow a board to use the default turbo ratio by not specifying
turbo_ratio_limit and turbo_ratio_limit_cores in the devicetree.cb.
TEST: Intel PTAT tool no longer complains about 0Mhz turbo frequency.
Change-Id: Ib8fbc78997fc7f8e6c80b2029d63b70f6117542e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Don't map more than 16MiB in ROM2 decode window when the SPI ROM
size is bigger than 16MiB.
TEST: amd/birman+ still boots with bigger SPI flash sizes.
Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit binds the cep_enable, enable_fast_vmode and
fast_vmode_i_trip voltage regulator SoC settings to the CepEnable,
EnableFastVmode and IccLimit UPDs respectively.
BUG=b:357011633
TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly
Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
It was accidentally deleted in a recent commit, but missed in review
since it is in a comment and not the actual acpigen code.
Change-Id: I0d28c2a67579a135e9002eaab9450353e8eec2d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to
Intel FSP repo does not ship all header files.
TEST=Build and boot on intel/archercity CRB
Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes child record count to 1 (i.e., compute die). The
number of crashlog agent/SRAM storage count is reduced in Crashlog
Discovery table (CRASHLOG_HEADER) for Panther Lake to 1 aka compute
die compared to MTL where crashlog units were compute die and GT die
source= 733648-LNLFAS-15.3.4,812562 PTL FAS 16.5.2 PTL
Dis-Aggreagation CrashLog
BUG=None
TEST=Build fatcat and verify the child record count
Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Controller2 and controller3 are disabled, so remove them from source
code.
BRANCH=rauru
BUG=b:389026545
TEST=Boot up to kernel
Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change eliminates the HAVE_FSP_LOGO_SUPPORT Kconfig option.
It was initially used to control BMP_LOGO selection within the FSP2.0
driver. However, upcoming refactoring will move BMP_LOGO and its
implementation to the `lib` directory therefore, BMP_LOGO can be
used by both FSP and non-FSP SoC platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I899bbfcf7e747abe69ff0866c4594a42278891b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86719
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add the MSG0 method to the ACP's SSDT entry, so that the ACP driver can
talk to a two different mailbox interfaces via this ACPI MSG0 method
interface. This is used by some drivers to configure the ACP's clock
source and to notify the PSP that the audio DSP firmware has been loaded
so that the PSP can validate the firmware and set the qualifier bit to
enable running it.
TEST=The AML code sequence written by this decompiles to the expected
ASL code and the driver is able to initialize the ACP correctly by
calling the MSG0 method twice with different parameters.
Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two ACPI methods to access a PSP mailbox interface via an SMN
register pair in the host bridge.
TEST=The AML code sequence written by this decompiles to the expected
ASL code.
Change-Id: I282f1fa2898f76659700450ee1f4b11f79d2d030
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SoCs require adding SoC-specific methods to the ACP's SSDT entry.
In order to not add SoC-specific code to the common ACP code, add the
'acp_soc_write_ssdt_entry' callback into the SoC-specific code and guard
it via the 'SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY' Kconfig
symbol to neither need weak functions or stubs in every SoC code.
Change-Id: I0ca5272d28938c8b90b645884a0d8b306a77d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add an ACPI OperationRegion to access an SMN access index/data register
pair in the root complex. To access the PCI config space registers, the
ECAM MMCONF MMIO region is used which matches the UEFI reference
implementation.
TEST=The AML code sequence written by this decompiles to the expected
ASL code.
Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IOT FSP binaries for MTL are available on github, so add FSP_TYPE_IOT
Kconfig option, select 'HAVE_INTEL_FSP_REPO', and add the paths for the
FSP headers and binary.
TEST=build/boot starlabs/starbook_mtl
Change-Id: I44ee923f4d1151f0e11104af7db53ce59551cf37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86611
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
All AMD SoCs from family 17h on, so all using a non-CAR configuration
to boot, have a reference clock of 100 MHz, so report this for all of
them in the SMBIOS tables.
Change-Id: I9573cbb8ec816c797314415d0c60c72abf23a094
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86690
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit fe107c1ad2.
I have strong doubts that this is Glinda-specific, so this likely should
have been made common after verifying.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib7282e2bec4d6aa5b74efa5621c825bc234cca82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86689
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 00b4a61dc5.
I have strong doubts that this is Glinda-specific, so this probably
should have been made common after verifying.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7fa0dca4c92f7bb0d49956aa9f1588b5fcba585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86688
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000
APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Generate a new TME key will cause S3 exit to fail, so
don't do it.
Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Allow boards to disable TME (total memory encryption) by guarding
selection of TME_KEY_REGENERATION_ON_WARM_BOOT on INTEL_TME.
This way, boards can set INTEL_TME to n in their Kconfig without
generating an unmet dependencies error.
The default behavior/Kconfig selections are unmodified with this change.
Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86621
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent PI releases have been distributing the ucode patch files as sbin
files instead of bin files. The sbin uses a 256 byte amd_fw_header to
wrap the bin file.
Offset 0x14 of the header is the size field. The can be extracted with
od to get the size of the ucode bin file. The bin file can then be
extracted with dd and placed in the build directory for inclusion as a
cbfs file.
In the case where both an sbin and bin ucode file are present, the bin
file will be added and a note will print at the start of the build about
the sbin file being skipped.
TEST=builds with only bin, only sbin, non-matching bin and sbin,
matching bin and sbin files
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68122
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds PAD_CFG_GPI_APIC_DRIVER macros to configure interrupt pad with
driver mode. This is needed when a PAD is configured as an interrupt
such that the corresponding GPI_IS status bit can be updated by the
host controller hardware.
BUG=none
TEST=Check a GPIO pad that is used as interrupt via GpioInt in the ACPI
device _CRS method and check the interrupt has been assigned in
/proc/interrupts.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86414
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel reference code for Thunder Peak increase the reset delay
to 160ms from 105ms seen on Jefferson Peak, Cyclone Peak and others.
For the sake of 110ms, use 160ms to cover all use cases.
Change-Id: I19c1bf7eeffa340e2564381a184ebfaca89bf364
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Check for the existence of BTRK method before attempting to
call it, as coreboot doesn't enforce its creation.
Change-Id: Ibb0dace635c6a014ce65ae3d1c96a92ff991ce5b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
