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soc/amd/cezanne/acpi: Add ACP SMN access interface

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Add two ACPI methods to access a PSP mailbox interface via an SMN
register pair in the host bridge.

TEST=The AML code sequence written by this decompiles to the expected
ASL code.

Change-Id: I282f1fa2898f76659700450ee1f4b11f79d2d030
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2025-02-16 22:13:14 +01:00
commit f60d630727
2 changed files with 42 additions and 0 deletions
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1
src/soc/amd/cezanne/Kconfig
View file

@ -27,6 +27,7 @@ config SOC_AMD_CEZANNE
select RTC
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACP_GEN1
select SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS

41
src/soc/amd/cezanne/acpi.c
View file

@ -4,6 +4,7 @@
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
#include <amdblocks/acp.h>
#include <amdblocks/acpi.h>
#include <amdblocks/cppc.h>
#include <amdblocks/cpu.h>
@ -91,3 +92,43 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
static void acp_soc_write_smn_access_methods(void)
{
acpigen_write_method_serialized("SMNR", 1);
acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
acpigen_write_return_namestr("\\_SB.PCI0.GNB.SMND");
acpigen_write_method_end();
acpigen_write_method_serialized("SMNW", 2);
acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
acpigen_write_store_op_to_namestr(ARG1_OP, "\\_SB.PCI0.GNB.SMND");
acpigen_write_method_end();
}
void acp_soc_write_ssdt_entry(const struct device *dev)
{
/*
* SMN interface using the SMN OperationRegion on the host bridge
*
* Scope (\_SB.PCI0.GP41.ACPD)
* {
* Method (SMNR, 1, Serialized)
* {
* Store (Arg0, \_SB.PCI0.GNB.SMNA)
* Return (\_SB.PCI0.GNB.SMND)
* }
*
* Method (SMNW, 2, Serialized)
* {
* Store (Arg0, \_SB.PCI0.GNB.SMNA)
* Store (Arg1, \_SB.PCI0.GNB.SMND)
* }
* }
*/
acpigen_write_scope(acpi_device_path(dev));
acp_soc_write_smn_access_methods();
acpigen_write_scope_end();
}