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soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

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This commit binds the cep_enable, enable_fast_vmode and
fast_vmode_i_trip voltage regulator SoC settings to the CepEnable,
EnableFastVmode and IccLimit UPDs respectively.

BUG=b:357011633
TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly

Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Jeremy Compostella 2024-11-12 10:32:43 -08:00 • committed by Matt DeVillier
commit bfeef0cc45
1 changed files with 9 additions and 2 deletions
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11
src/soc/intel/pantherlake/romstage/fsp_params.c
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@ -285,8 +285,15 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,
static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_pantherlake_config *config)
{
for (size_t i = 0; i < ARRAY_SIZE(m_cfg->EnableFastVmode); i++)
m_cfg->EnableFastVmode[i] = 0;
for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) {
if (config->cep_enable[i]) {
m_cfg->CepEnable[i] = config->cep_enable[i];
if (config->enable_fast_vmode[i]) {
m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i];
m_cfg->IccLimit[i] = config->fast_vmode_i_trip[i];
}
}
}
}
#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)