erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/mtl/acpi: add entries for HEC1 and SRAM to DSDT

Browse source 
HEC1 and SRAM are defined in src/soc/intel/meteorlake/chipset.cb:

device pci 16.0 alias heci1 on  end
device pci 14.2 alias pmc_shared_sram off end

Add entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors
in the kernel dmesg log, and add entries to soc_acpi_name() to ensure
that these names are returned during acpi_device_path() calls.

TEST=Build/boot Linux 6.x on screebo to confirm errors are not seen.

Change-Id: Id79054d2cb56daae238ac562b7b6c204926cdced
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86797
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Matt DeVillier 2025-03-07 18:18:53 -06:00
commit e22ff257d6
2 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/meteorlake/acpi/southbridge.asl
View file

@ -43,6 +43,12 @@
/* USB XHCI 0:14.0 */
#include "xhci.asl"
/* PMC Shared SRAM 0:14.2 */
#include <soc/intel/common/block/acpi/acpi/sram.asl>
/* CSE/HECI #1 0:16.0 */
#include <soc/intel/common/block/acpi/acpi/heci.asl>
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>

2
src/soc/intel/meteorlake/chip.c
View file

@ -116,7 +116,9 @@ const char *soc_acpi_name(const struct device *dev)
case PCI_DEVFN_HDA: return "HDAS";
case PCI_DEVFN_SMBUS: return "SBUS";
case PCI_DEVFN_GBE: return "GLAN";
case PCI_DEVFN_SRAM: return "SRAM";
case PCI_DEVFN_SPI: return "FSPI";
case PCI_DEVFN_CSE: return "HECI";
}
printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));