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Revert "soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs"

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This reverts commit 491afc3cc7.

Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and
'PchPciePowerGating' UPDs are also available on ADL-N.

Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Filip Brozovic 2025-03-01 23:34:18 +01:00 • committed by Matt DeVillier
commit e6c6606884
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/alderlake/fsp_params.c
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@ -922,7 +922,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
}
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
#if CONFIG(FSP_TYPE_IOT)
/*
* Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
* The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1