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soc/mediatek/mt8196: Adjust thermal trip point parameters

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Adjust thermal trip point parameters so the thermal can trigger the
interrupt at the expected trip point.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up and check temperature in coreboot log:
[INFO ]  [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523)
[INFO ]  [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715)
[INFO ]  [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717)
[INFO ]  [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350)
[INFO ]  [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593)
[INFO ]  [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)

Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86552
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Zhaoqing Jiu 2025-02-20 15:37:47 +08:00 • committed by Yidi Lin
commit 1633ae8378
1 changed files with 2 additions and 2 deletions
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4
src/soc/mediatek/mt8196/include/soc/thermal_internal.h
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@ -171,8 +171,8 @@ check_member(mtk_thermal_controller_regs, lvtsspare, 0x0f0);
#define AP_RST_SET (INFRACFG_AO_SEC_BASE + 0xf30)
#define AP_RST_CLR (INFRACFG_AO_SEC_BASE + 0xf34)
#define LVTS_COF_T_SLP_GLD 358830
#define LVTS_COF_COUNT_R_GLD 34389
#define LVTS_COF_T_SLP_GLD 391460
#define LVTS_COF_COUNT_R_GLD 34412
#define LVTS_COF_T_CONST_OFS 0
#define DEFAULT_EFUSE_GOLDEN_TEMP 60