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soc/amd/common/block/lpc: Limit ROM2 to 16MiB

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Don't map more than 16MiB in ROM2 decode window when the SPI ROM
size is bigger than 16MiB.

TEST: amd/birman+ still boots with bigger SPI flash sizes.

Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2025-02-23 15:34:17 +01:00 • committed by Matt DeVillier
commit 97bf77e52e
1 changed files with 5 additions and 3 deletions
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8
src/soc/amd/common/block/lpc/lpc_util.c
View file

@ -239,7 +239,7 @@ void lpc_tpm_decode_spi(void)
}
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
* Enable up to 16MB (LPC) ROM access at 0xFF000000 - 0xFFFFFFFF.
*
* Hardware should enable LPC ROM by pin straps. This function does not
* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
@ -276,9 +276,11 @@ void lpc_enable_rom(void)
* 0xfff0(0000): 1MB
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
* 0xff00(0000): 16MB
*
*/
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START,
0x10000 - (MIN(CONFIG_COREBOOT_ROMSIZE_KB, 16384) >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);