soc/mediatek/mt8196: Support 512 bytes EDID
Refine dptx_get_edid function to read extension edid to bring up 2.8k 120hz OLED panel. BRANCH=rauru BUG=b:392040003 TEST=check edp training pass and show log: EQ training pass Change-Id: If35782950ae02d892ea697580fa4991595c21533 Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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2 changed files with 28 additions and 5 deletions
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@ -73,17 +73,38 @@ bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
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int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
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{
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int ret;
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u8 edid[ONE_BLOCK_SIZE];
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u8 edid[EDID_BUF_SIZE];
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u8 tmp = 0;
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u8 extblock = 0;
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size_t total_size;
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dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp);
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for (tmp = 0; tmp < ONE_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
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/* Read 1st block */
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for (tmp = 0; tmp < EDID_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
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dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ,
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0x50, DP_AUX_MAX_PAYLOAD_BYTES,
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edid + tmp * 16);
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edid + tmp * DP_AUX_MAX_PAYLOAD_BYTES);
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ret = decode_edid(edid, ONE_BLOCK_SIZE, out);
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extblock = edid[EDID_EXT_BLOCK_COUNT];
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total_size = EDID_BLOCK_SIZE * (1 + extblock);
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if (total_size > EDID_BUF_SIZE) {
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printk(BIOS_WARNING, "The edid block size(%zu) is larger than %u bytes\n",
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total_size, EDID_BUF_SIZE);
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printk(BIOS_WARNING, "Read first %u bytes only\n", EDID_BUF_SIZE);
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total_size = EDID_BUF_SIZE;
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}
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if (total_size > EDID_BLOCK_SIZE) {
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for (tmp = EDID_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES;
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tmp < total_size / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
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dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ,
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0x50, DP_AUX_MAX_PAYLOAD_BYTES,
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edid + tmp * DP_AUX_MAX_PAYLOAD_BYTES);
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}
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ret = decode_edid(edid, total_size, out);
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if (ret != EDID_CONFORMANT) {
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printk(BIOS_ERR, "failed to decode edid(%d).\n", ret);
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return -1;
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@ -8,7 +8,8 @@
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#define ENABLE_DPTX_EF_MODE 0x1
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#define DPTX_AUX_SET_ENAHNCED_FRAME 0x80
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#define ONE_BLOCK_SIZE 128
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#define EDID_BLOCK_SIZE 128
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#define EDID_BUF_SIZE (EDID_BLOCK_SIZE * 4)
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#define DP_LINK_CONSTANT_N_VALUE 0x8000
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#define DP_LINK_STATUS_SIZE 6
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@ -38,6 +39,7 @@
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#define DP_EDP_14 0x03
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#define DP_EDP_14a 0x04
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#define DP_EDP_14b 0x05
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#define EDID_EXT_BLOCK_COUNT 0x7E
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/* Receiver Capability */
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#define DP_DPCD_REV 0x000
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