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src/soc/intel/adl: Add EnableTcssCovTypeA and MappingPchXhciUsbA

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Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ]  EnableTcssCovTypeA[0]= 0x00000000
[SPEW ]  MappingPchXhciUsbA[0]= 0x00000000
[SPEW ]  EnableTcssCovTypeA[1]= 0x00000001
[SPEW ]  MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf

BUG=b:400809281
TEST=Able to build and boot google/Riven

Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lawrence 2025-03-10 16:53:21 +08:00 • committed by Matt DeVillier
commit 19deb5e5f8
2 changed files with 16 additions and 0 deletions
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9
src/soc/intel/alderlake/chip.h
View file

@ -799,6 +799,15 @@ struct soc_intel_alderlake_config {
PD_TIER_PREMIUM = 25000,
PD_TIER_VOLUME = 27000
} vccin_aux_imon_iccmax;
/* Enable / Disable(default) Type C Port x Convert to TypeA */
bool enabletcsscovtypea[4];
/*
* PCH xhci port x for Type C Port x mapping.
* Input PCH xhci port x for Type C Port 0 mapping.
*/
uint8_t mappingpchxhciusba[4];
};
typedef struct soc_intel_alderlake_config config_t;

7
src/soc/intel/alderlake/fsp_params.c
View file

@ -650,6 +650,13 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
s_cfg->UsbTcPortEn |= BIT(i);
}
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
if (config->enabletcsscovtypea[i]) {
s_cfg->EnableTcssCovTypeA[i] = config->enabletcsscovtypea[i];
s_cfg->MappingPchXhciUsbA[i] = config->mappingpchxhciusba[i];
}
}
s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
}