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soc/mediatek/mt8196: Save HW protect temperature to SRAM

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It will restore the HW protection settings based on the data saved in
the SRAM, after the system suspends and resumes.

BRANCH=rauru
BUG=b:389026545
TEST=Boot up and check temperature in coreboot log:
[INFO ]  [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523)
[INFO ]  [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715)
[INFO ]  [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717)
[INFO ]  [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059)
[INFO ]  [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350)
[INFO ]  [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593)
[INFO ]  [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318
[INFO ]  lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)

Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: Ib714c297871132907e286536c4b3aea1532f3869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86551
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Zhaoqing Jiu 2025-02-21 16:23:20 +08:00 • committed by Yidi Lin
commit 1faea7389c
4 changed files with 30 additions and 0 deletions
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2
src/soc/mediatek/mt8196/include/soc/thermal.h
View file

@ -5,5 +5,7 @@
void thermal_sram_init(void);
void thermal_init(void);
void thermal_write_reboot_temp_sram(uint32_t value);
void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value);
#endif /* SOC_MEDIATEK_MT8196_THERMAL_H */

2
src/soc/mediatek/mt8196/include/soc/thermal_internal.h
View file

@ -55,6 +55,8 @@ struct lvts_thermal_controller {
size_t ts_number;
int reboot_temperature;
int dominator_ts_idx;
unsigned int reboot_msr_sram_idx;
bool has_reboot_temp_sram;
struct lvts_thermal_controller_speed speed;
struct mtk_thermal_controller_regs *regs;
};

8
src/soc/mediatek/mt8196/thermal.c
View file

@ -43,6 +43,8 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
.ts_number = 4,
.reboot_temperature = 118800,
.dominator_ts_idx = 0,
.reboot_msr_sram_idx = 0,
.has_reboot_temp_sram = true,
.speed = {
.group_interval_delay = 0x7fff,
.period_unit = 0x001,
@ -57,6 +59,8 @@ static const struct lvts_thermal_controller lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM]
.ts_number = 4,
.reboot_temperature = 118800,
.dominator_ts_idx = 0,
.reboot_msr_sram_idx = 1,
.has_reboot_temp_sram = false,
.speed = {
.group_interval_delay = 0x7fff,
.period_unit = 0x001,
@ -543,6 +547,10 @@ static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller
raw_high = MAX(raw_high, raw);
}
thermal_write_reboot_msr_sram(tc->reboot_msr_sram_idx, raw_high);
if (tc->has_reboot_temp_sram)
thermal_write_reboot_temp_sram(tc->reboot_temperature);
setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF);
/* disable trigger SPM interrupt */
write32(&tc->regs->lvtsmonint_0, 0);

18
src/soc/mediatek/mt8196/thermal_sram.c
View file

@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#include <arch/cache.h>
#include <assert.h>
#include <soc/thermal_internal.h>
#include <string.h>
/* SRAM for Thermal */
#define THERMAL_SRAM_BASE (_mcufw_reserved + 0x1000)
#define THERMAL_SRAM_LEN 0x400
#define THERMAL_REBOOT_TEMP_SRAM_OFFSET 0x39C
#define THERMAL_REBOOT_MSR_SRAM_OFFSET 0x340
#define THERMAL_REBOOT_MSR_SRAM_LEN (6 * 4)
static void thermal_cls_sram(void)
{
@ -59,3 +63,17 @@ void thermal_sram_init(void)
thermal_stat_cls_sram();
thermal_gpu_stat_cls_sram();
}
void thermal_write_reboot_temp_sram(uint32_t value)
{
write32(THERMAL_SRAM_BASE + THERMAL_REBOOT_TEMP_SRAM_OFFSET, value);
}
void thermal_write_reboot_msr_sram(unsigned int idx, uint32_t value)
{
unsigned int offset = 0;
assert((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN);
offset = THERMAL_REBOOT_MSR_SRAM_OFFSET + idx * 4;
write32(THERMAL_SRAM_BASE + offset, value);
}