The MFGPLL_*_BASE addresses are based on MFGSYS_BASE (0x40000000)
instead of IO_PHYS (0x10000000). Rewrite the address calculation for
readability.
Also rename these macros to MFG_PLL_* to make them consistent with other
macros to be added in CB:85654.
Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85740
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces this file to
"GPL-2.0-only OR MIT" license for better code re-use in other open
source software stack.
BUG=b:379008996
BRANCH=none
TEST=build pass
Change-Id: I2821a8c097b8d22e1aa91b316ae0fdce80f342de
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85723
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add watchdog support for MT8189.
BUG=b:379008996
BRANCH=none
TEST=build pass and WDT makes DUT reboot when MTK_WDT_MODE_ENABLE is
set.
Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85678
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting from MT8196, MediaTek platform introudces a new blob named
MediaTek firmware support package (mtk-fsp). The features of mtk-fsp
include but not limit to,
- Security settings, e.g: Device Access Proctection Control, Security
Memory Protection Unit.
- Initialization for advanced CPU frequency control.
This patch implements APIs for
1) Exchanging data between coreboot and mtk-fsp.
2) Loading and running the mtk-fsp blob at a specific bootstage.
BUG=b:373797027
TEST=emerge-rauru coreboot; Run mock blob and return from mock blob.
Change-Id: Idef3518f9763fe5f74adb459c137db164563e483
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85665
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update timer macro name for common.
The new ICs (e.g. mt8196, mt8189) will no longer use GPT. In order
to improve code readability, replace GPT_MHZ with TIMER_MHZ for
existing SoCs.
BUG=b:379008996
BRANCH=none
TEST=Build pass, Macro name is correct.
Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4
Signed-off-by: Ke Zheng <ot_ke.zheng@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85681
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM
and fix the SPM register definitions. SPM needs its own firmware to
enable SPM suspend/resume function which turns off several resources
such as DRAM/mainpll/26M clk when linux system suspends.
coreboot log:
CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c
mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt)
TEST=build pass
BUG=348147674
Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85599
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This change adds the ACPI name "SPI2" for the GSPI2 device
in the Panther Lake SOC.
Replace space with tab for PCI_DEVFN_GSPI2 macro.
w/o this patch:
[ERROR] Missing ACPI Name for PCI: 00:12.6
[ERROR] Missing ACPI Name for PCI: 00:12.6
w/ this patch:
No error
Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85712
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.
BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.
Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add new folder and basic drivers for Mediatek SoC 'MT8189'.
Also enable UART and ARM arch timer.
This commit includes the necessary initialization files for MT8189,
which cannot be shared with other existing SoCs.
The modules included are:
- Memory layout: MT8189 has only 64KB of SRAM, differing in space
allocation compared to other SoCs.
- PLL: Different SoCs have different PLL designs. In this commit,
we provide the most basic settings, with more configurations to
be added in future commits.
- Timer: MT8189 uses timer v2, unlike other SoCs which use timer v1.
- SPI: The SPI driver for different SoCs varies depending on the GPIO/
PIN MUX used. In this commit, we provide the most basic settings,
with more configurations to be added in future commits.
- EMI: MT8189 uses common EMI code along with MT8189-specific
'dram_parameter.h'. This commit provides an EMI stub to ensure
coreboot builds successfully. Future DRAM-related commits will
utilize the common EMI code.
BUG=b:379008996
BRANCH=none
TEST=saw the coreboot uart log to bootblock
Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85616
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek pwrsel (Power Select) is mainly used to reduce power
consumption, controlled by mcupm.
BUG=b:317009620
TEST=Build pass
Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds an ACPI method to get the LPC Generic Memory Range
(LGMR) address. This is necessary for platforms that need to access
the LGMR from OS driver.
The new method, called GLGM, reads the LGMR address from the LPC PCI
configuration space (offset 0x98) and returns it as a 32-bit value.
BUG=b:354066052
TEST=Able to build and boot google/brox.
Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85602
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8196's SPM_SYSTEM_BASE_OFFSET has a different offset due to the
hardware design. To avoid adding a new kconfig for differentiation,
migrate this definition into SoC specific value.
BUG=none
TEST=emerge-geralt coreboot && emerge-corsola coreboot
Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85625
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The init flow in `spm_init_pcm_register` and `spm_kick_pcm_to_run` is
simplified on MT8196. And MT8196 does not have corresponded registers
used by these two functions. Therefore, move these two function to a
separated file and simply name it as spm_v1.c.
BUG=none
TEST=emerge-geralt coreboot && emerge-corsola coreboot
Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85623
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rauru reference design has SD card interfaces, so we have to configure
it in ramstage.
Implement msdc.c (memory and SD Card controller) to place the SD card
drivers.
This implementation is based on chapter 10.3 in MT8196 Functional
Specification.
TEST=Build pass
BUG=b:317009620
Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85564
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug.
Rename VLPCFG_BASE to VLP_CFG_BASE.
TEST=Build pass, When we encounter a bus hang and HW watchdog triggers
a reset to the platform, the tracker will print the
latched information:
[INFO ] **Dump %s aw debug register start**
[INFO ] xxxxxx, 0x1c600000, 0x0, 63
This means that the 63rd entry latch accessing 0x1c600000 has a bus
timeout.
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84929
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMinfra is the Multimedia Infrastructure. All the Multimedia modules
depend on it. This file adds some initial settings for MMinfra.
Test=Build pass
BUG=b:317009620
Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.corp-partner.google.com>
Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Make use of exception handling in every stage. Additionally this
enables breakpoints in all stages, making NULL dereferences and
stack overflows easier to detect.
TEST: Stack canary exceptions are seen in romstage on ibm/sbp1.
Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85569
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage
hook and introduce early_pch_init() to do PCH init in romstage before
FSP-M runs.
Move PCH specific code into early_pch_init and call it from common code.
Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85505
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no
official bit in the IFD to disable it. The device is disabled
early to:
1. Prevent FSP from seeing the device being present. It could keep
an internal state that the device is working.
2. Prevent FSP-M from trying to detect codecs. This would increase
boot time.
3. Prevent FSP from becoming confused or crash when the device is
suddently missing as disabled by a ramstage PCI driver.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85496
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Route IRQ for on-chip end-points only (e.g. 00:1f.4
i801_smbus)
IRQ routing for devices under root ports needs additional
swizzle per decided by root port configurations, which will
postponed to later till there is actual usage.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ImguClkOutEn parameters are required in pantherlake, therefore,
avoid disabling the IMGU CLKOUT FSP UPDs.
BUG=b:381044394
TEST=Able to see FSP-M UPDs for google/fatcat where IMGU CLKOUTs are
not disabled with this patch.
Change-Id: Ieb022e6dc0b64106ff30f56cd17f9f219276785f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85588
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and
`DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options
for the Pantherlake SOC.
These options are causing false positive stack overflow detections,
leading to unnecessary debugging.
w/o this patch:
stack corruption before for verstage and romstage early.
Failed to create address zero instruction fetch breakpoint
Failed to create stack canary breakpoint
...
...
Stack corruption detected at rip: 0xf983007a
Stack corruption detected at rip: 0xf983007a
Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85584
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to its
SRAM space and then enable it.
It takes 20 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314
mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes)
TEST=can see the sspm logs.
BUG=b:372173976
Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0
Signed-off-by: Kenji Yu <kenji.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Implement PMIF driver for communication between SoC and PMIC. Develop
SPMI driver for communication over the SPMI bus. Add necessary
configurations and base addresses to support PMIF.
TEST=build pass, check boot log with:
[INFO ] mtk_pmif_init: SPMI_MASTER_1, 0
[INFO ] mtk_pmif_init: SPMI_MASTER_0, 0
BUG=b:317009620
Change-Id: I232015f45735ee5278b09d0352410617a1565177
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85126
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add GBTR Method, which gets the state of the RF Kill pin. Unlike
the VGPIO, this can be used for both CNVi and full PCI wireless
cards.
Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek booker (the customized ARM CI-700) is a high-performance
interconnect architecture designed for multi-core processor systems,
providing high bandwidth, low latency data transfer. And booker mainly
uses CHI protocol, but doesn't support coherence (which is achieved
through ACP solution). Additionally, the booker also uses other
protocols such as AXI, which translates CHI transactions into EMI's AXI
transactions.
Currently, the mt8196 booker only uses the functions of SLC CMO routing.
If downstream SLC needs CMO command propagation from the DSU, it is
needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of
each SBSX node in order to propagate the CMO command.
Increase the bootblock size from 75K to 78K to support booker.
TEST=build pass, check boot log with:
[booker_init] AP hash rule: 0xbe00.
BUG=b:317009620
Signed-off-by: Dehui Sun <dehui.sun@mediatek.corp-partner.google.com>
Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move PCU specific code into separate files:
- PCUs registers are now locked by the PCI driver final call
- set_bios_init_completion() is not part of PCU1 driver
- Integrate config_reset_cpl3_csrs() into PCU driver
TEST: Still boots on ocp/tiogapass.
Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)) returns
the register content and should not be compared with
PCI_ITSS_PIR(0) which is an address offset. By now, we assume the
returned PIR is always effective and usable.
Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85284
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add const qualifer for itss_get_on_chip_dev_pirq and
itss_soc_get_on_chip_dev_pir so that these ops could be used for
both struct device * input and const struct device * input.
Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will
be executed in common pch/lockdown firstly. Remove xeon_sp layer
lpc_lockdown_config() to avoid duplication.
The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c:
static void platform_lockdown_config(void *unused)
{
int chipset_lockdown;
chipset_lockdown = get_lockdown_config();
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);
/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);
...
}
Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85286
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop function fast_spi_set_vcl as the same code already exists
as fast_spi_vscc0_lock() and is already run on xeon_sp.
Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
