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soc/intel/ptl: Enable UFS functionality by adding IRQ programming

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This commit adds the necessary IRQ programming for the UFS controller,
addressing an issue where the device was not operational after booting
to the OS.

BUG=b:382243957
TEST=Built and booted google/fatcat successfully, verifying UFS
functionality.

with this patch

```
[SPEW ]   Interrupt assignment:
[SPEW ]    Dxx:Fx   INTx  IRQ
[SPEW ]    D23:F0    1    018
```

Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85536
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-12-09 13:15:28 +05:30
commit fbacae625a
1 changed files with 8 additions and 0 deletions
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8
src/soc/intel/pantherlake/fsp_params.c
View file

@ -199,6 +199,14 @@ static const struct slot_irq_constraints irq_constraints[] = {
ANY_PIRQ(PCI_DEVFN_CSE_4),
},
},
#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
{
.slot = PCI_DEV_SLOT_UFS,
.fns = {
ANY_PIRQ(PCI_DEVFN_UFS),
},
},
#endif
{
.slot = PCI_DEV_SLOT_SIO1,
.fns = {