soc/mediatek/common: Move some functions to spm_v1.c

The init flow in `spm_init_pcm_register` and `spm_kick_pcm_to_run` is
simplified on MT8196. And MT8196 does not have corresponded registers
used by these two functions. Therefore, move these two function to a
separated file and simply name it as spm_v1.c.

BUG=none
TEST=emerge-geralt coreboot && emerge-corsola coreboot

Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85623
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/include/soc/spm_common.h

@@ -27,5 +27,8 @@ void spm_reset_and_init_pcm(void);
 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
 void spm_extern_initialize(void);
 int spm_init(void);
+void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl);
+void spm_init_pcm_register(void);
+void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl);
 
 #endif  /* SOC_MEDIATEK_SPM_COMMON_H */

src/soc/mediatek/common/spm.c

@@ -51,22 +51,7 @@ static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
 	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 }
 
-static void spm_init_pcm_register(void)
-{
-	/* Init r0 with POWER_ON_VAL0 */
-	write32(&mtk_spm->pcm_reg_data_ini,
-		read32(&mtk_spm->spm_power_on_val0));
-	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
-	write32(&mtk_spm->pcm_pwr_io_en, 0);
-
-	/* Init r7 with POWER_ON_VAL1 */
-	write32(&mtk_spm->pcm_reg_data_ini,
-		read32(&mtk_spm->spm_power_on_val1));
-	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
-	write32(&mtk_spm->pcm_pwr_io_en, 0);
-}
-
-static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
+void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
 {
 	u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
 
@@ -86,31 +71,6 @@ static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
 	write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
 }
 
-static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
-{
-	/* Waiting for loading SPMFW done*/
-	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
-		;
-
-	/* Init register to match PCM expectation */
-	write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
-	write32(&mtk_spm->spm_bus_protect2_mask_b,
-		SPM_BUS_PROTECT2_MASK_B_DEF);
-	write32(&mtk_spm->pcm_reg_data_ini, 0);
-
-	spm_set_pcm_flags(pwrctrl);
-
-	/* Kick PCM to run (only toggle PCM_KICK) */
-	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
-
-	/* Reset md32pcm */
-	SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
-			MD32PCM_CFGREG_SW_RSTN_RESET, 1);
-
-	/* Waiting for SPM init done */
-	udelay(SPM_INIT_DONE_US);
-}
-
 static void spm_parse_firmware(struct mtk_mcu *mcu)
 {
 	size_t file_size, copy_size;

src/soc/mediatek/common/spm_v1.c

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/spm.h>
+#include <delay.h>
+
+void spm_init_pcm_register(void)
+{
+	/* Init r0 with POWER_ON_VAL0 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val0));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* Init r7 with POWER_ON_VAL1 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val1));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+}
+
+void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
+{
+	/* Waiting for loading SPMFW done*/
+	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
+		;
+
+	/* Init register to match PCM expectation */
+	write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
+	write32(&mtk_spm->spm_bus_protect2_mask_b,
+		SPM_BUS_PROTECT2_MASK_B_DEF);
+	write32(&mtk_spm->pcm_reg_data_ini, 0);
+
+	spm_set_pcm_flags(pwrctrl);
+
+	/* Kick PCM to run (only toggle PCM_KICK) */
+	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* Reset md32pcm */
+	SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
+			MD32PCM_CFGREG_SW_RSTN_RESET, 1);
+
+	/* Waiting for SPM init done */
+	udelay(SPM_INIT_DONE_US);
+}

src/soc/mediatek/mt8186/Makefile.mk

@@ -50,7 +50,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
-ramstage-y += ../common/spm.c spm.c
+ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
 ramstage-y += ../common/sspm.c
 ramstage-y += ../common/tps65132s.c
 ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c

src/soc/mediatek/mt8188/Makefile.mk

@@ -56,7 +56,7 @@ ramstage-y += ../common/pmif_spi.c pmif_spi.c
 ramstage-y += ../common/pmif_spmi.c pmif_spmi.c
 ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c
-ramstage-y += ../common/spm.c spm.c
+ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
 ramstage-y += ../common/sspm.c
 ramstage-y += ../common/tps65132s.c
 ramstage-y += ../common/usb.c usb.c

src/soc/mediatek/mt8192/Makefile.mk

@@ -49,7 +49,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c ../common/pmif_init.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c
-ramstage-y += ../common/spm.c spm.c
+ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
 ramstage-y += ../common/sspm.c
 ramstage-y += ../common/ufs.c
 ramstage-y += ../common/usb.c usb.c

src/soc/mediatek/mt8195/Makefile.mk

@@ -65,7 +65,7 @@ ramstage-y += ../common/pll.c pll.c
 ramstage-y += ../common/pmif.c ../common/pmif_init.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
 ramstage-y += soc.c
-ramstage-y += ../common/spm.c spm.c
+ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
 ramstage-y += ../common/sspm.c
 ramstage-y += ../common/ufs.c
 ramstage-y += ../common/usb.c usb.c