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intel/common/block: Program the right power_limits_config entry

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When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.

This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.

All data structures utilized by this function are updated accordingly.

BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.

Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-12-09 20:03:50 +05:30
commit 6d3346068b
7 changed files with 15 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
View file

@ -41,6 +41,7 @@ const struct cpu_tdp_power_limits limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
.cpu_tdp = 28,
.power_limits_index = MTL_P_682_482_CORE,
.pl1_min_power = 19000,
.pl1_max_power = 28000,
.pl2_min_power = 64000,
@ -50,6 +51,7 @@ const struct cpu_tdp_power_limits limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
.cpu_tdp = 28,
.power_limits_index = MTL_P_682_482_CORE,
.pl1_min_power = 19000,
.pl1_max_power = 28000,
.pl2_min_power = 64000,

4
src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
View file

@ -15,6 +15,7 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
@ -24,6 +25,7 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
@ -36,6 +38,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
@ -45,6 +48,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,

2
src/mainboard/google/rex/variants/deku/ramstage.c
View file

@ -14,6 +14,7 @@ const struct cpu_tdp_power_limits variant_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
.cpu_tdp = 28,
.power_limits_index = MTL_P_682_482_CORE,
.pl1_min_power = 19000,
.pl1_max_power = 28000,
.pl2_min_power = 64000,
@ -23,6 +24,7 @@ const struct cpu_tdp_power_limits variant_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
.cpu_tdp = 28,
.power_limits_index = MTL_P_682_482_CORE,
.pl1_min_power = 19000,
.pl1_max_power = 28000,
.pl2_min_power = 64000,

2
src/mainboard/google/rex/variants/screebo/variant.c
View file

@ -35,6 +35,7 @@ const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
@ -44,6 +45,7 @@ const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,

2
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <chip.h>
#include <device/pci_ids.h>
#include <intelblocks/power_limit.h>
@ -13,6 +14,7 @@ const struct cpu_tdp_power_limits limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.power_limits_index = MTL_P_282_242_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,

1
src/soc/intel/common/block/include/intelblocks/power_limit.h
View file

@ -45,6 +45,7 @@ u8 get_cpu_tdp(void);
struct cpu_tdp_power_limits {
uint16_t mch_id;
uint8_t cpu_tdp;
uint32_t power_limits_index;
unsigned int pl1_min_power;
unsigned int pl1_max_power;
unsigned int pl2_min_power;

3
src/soc/intel/common/block/power_limit/power_limit.c
View file

@ -268,7 +268,8 @@ void variant_update_cpu_power_limits(const struct cpu_tdp_power_limits *limits,
} else {
struct dptf_power_limits *settings = &config->controls.power_limits;
config_t *conf = config_of_soc();
struct soc_power_limits_config *soc_config = conf->power_limits_config;
struct soc_power_limits_config *soc_config =
&conf->power_limits_config[limits[index].power_limits_index];
settings->pl1.min_power = limits[index].pl1_min_power;
settings->pl1.max_power = limits[index].pl1_max_power;
settings->pl2.min_power = limits[index].pl2_min_power;