soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability
Update timer macro name for common. The new ICs (e.g. mt8196, mt8189) will no longer use GPT. In order to improve code readability, replace GPT_MHZ with TIMER_MHZ for existing SoCs. BUG=b:379008996 BRANCH=none TEST=Build pass, Macro name is correct. Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4 Signed-off-by: Ke Zheng <ot_ke.zheng@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85681 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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5 changed files with 5 additions and 5 deletions
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@ -7,7 +7,7 @@
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#include <soc/timer_common.h>
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#include <types.h>
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#define GPT_MHZ 13
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#define TIMER_MHZ 13
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struct mtk_gpt_regs {
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u32 reserved1[24];
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@ -7,7 +7,7 @@
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#include <soc/timer_common.h>
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#include <types.h>
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#define GPT_MHZ 13
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#define TIMER_MHZ 13
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enum {
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TIE_0_EN = 1 << 3,
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@ -27,7 +27,7 @@ static uint64_t timer_raw_value(void)
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void timer_monotonic_get(struct mono_time *mt)
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{
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mono_time_set_usecs(mt, timer_raw_value() / GPT_MHZ);
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mono_time_set_usecs(mt, timer_raw_value() / TIMER_MHZ);
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}
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void init_timer(void)
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@ -18,5 +18,5 @@ void timer_prepare(void)
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*/
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write32(&mt8173_mcucfg->xgpt_idx, 0);
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/* Set clock mode to 13Mhz and enable XGPT */
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write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT_MHZ) << 8)));
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write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / TIMER_MHZ) << 8)));
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}
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@ -9,5 +9,5 @@ void init_timer(void)
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{
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timer_prepare();
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raw_write_cntfrq_el0(GPT_MHZ * MHz);
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raw_write_cntfrq_el0(TIMER_MHZ * MHz);
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}
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