soc/mediatek/mt8196: Initialize SSPM

SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to its
SRAM space and then enable it.

It takes 20 ms to load sspm.bin.

coreboot logs:
CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314
mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes)

TEST=can see the sspm logs.
BUG=b:372173976

Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0
Signed-off-by: Kenji Yu <kenji.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/common/include/soc/sspm.h

@@ -10,5 +10,8 @@ struct sspm_regs {
 	u32 sw_rstn;
 };
 static struct sspm_regs *const sspm_reg = (void *)SSPM_CFG_BASE;
+
+void sspm_enable_sram(void);
 void sspm_init(void);
+
 #endif  /* SOC_MEDIATEK_COMMON_SSPM_H */

src/soc/mediatek/common/sspm.c

@@ -16,8 +16,15 @@ static struct mtk_mcu sspm = {
 	.reset = reset_sspm,
 };
 
+__weak void sspm_enable_sram(void)
+{
+	/* do nothing. */
+}
+
 void sspm_init(void)
 {
+	sspm_enable_sram();
+
 	sspm.load_buffer = _dram_dma;
 	sspm.buffer_size = REGION_SIZE(dram_dma);
 

src/soc/mediatek/mt8196/Kconfig

@@ -38,4 +38,11 @@ config DPM_PM_FIRMWARE
 	default "dpm.pm"
 	help
 	  The file name of the MediaTek DPM PM firmware.
+
+config SSPM_FIRMWARE
+	string
+	default "sspm.bin"
+	help
+	  The file name of the MediaTek SSPM firmware.
+
 endif

src/soc/mediatek/mt8196/Makefile.mk

@@ -47,6 +47,7 @@ ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c
 ramstage-y += ../common/mt6363.c mt6363.c
 ramstage-y += ../common/mt6363_sdmadc.c
 ramstage-y += soc.c
+ramstage-y += ../common/sspm.c sspm_sram.c
 ramstage-y += ../common/pmif_clk.c pmif_clk.c
 ramstage-y += ../common/pmif.c pmif_init.c
 ramstage-y += pmif_spmi.c
@@ -61,7 +62,8 @@ MT8196_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8196
 
 mcu-firmware-files := \
 	$(CONFIG_DPM_DM_FIRMWARE) \
-	$(CONFIG_DPM_PM_FIRMWARE)
+	$(CONFIG_DPM_PM_FIRMWARE) \
+	$(CONFIG_SSPM_FIRMWARE)
 
 $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
 	$(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \

src/soc/mediatek/mt8196/include/soc/addressmap.h

@@ -153,6 +153,8 @@ enum {
 	SPMI_MST_BASE		= IO_PHYS + 0x0C01C000,
 	SPMI_MST_P_BASE		= IO_PHYS + 0x0C01C800,
 	VLP_AO_DEBUG_BASE	= IO_PHYS + 0x0C031000,
+	SSPM_SRAM_BASE		= IO_PHYS + 0x0C300000,
+	SSPM_CFG_BASE		= IO_PHYS + 0x0C340000,
 	SYSTIMER_BASE		= IO_PHYS + 0x0C400000,
 	VLP_TRACKER_BASE        = IO_PHYS + 0x0C4E0000,
 	MMVOTE_MMSYS_CONFIG_BASE	= IO_PHYS + 0x12000000,

src/soc/mediatek/mt8196/soc.c

@@ -6,6 +6,7 @@
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
 #include <soc/pcie.h>
+#include <soc/sspm.h>
 #include <soc/symbols.h>
 #include <symbols.h>
 
@@ -26,6 +27,7 @@ static void soc_read_resources(struct device *dev)
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
+	sspm_init();
 }
 
 static struct device_operations soc_ops = {

src/soc/mediatek/mt8196/sspm_sram.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/sspm.h>
+
+#define SSPM_SRAM_CON		(SPM_BASE + 0xEE4)
+#define SPM_PRJ_CODE		0xB160001
+#define SSPM_SRAM_SLEEP_B	0x10
+#define SSPM_SRAM_ISOINT_B	0x2
+
+void sspm_enable_sram(void)
+{
+	write32p(SPM_BASE, SPM_PRJ_CODE);
+	write32p(SSPM_SRAM_CON, SSPM_SRAM_SLEEP_B | SSPM_SRAM_ISOINT_B);
+}