soc/mediatek/mt8196: Add pwrsel driver

The MediaTek pwrsel (Power Select) is mainly used to reduce power
consumption, controlled by mcupm.

BUG=b:317009620
TEST=Build pass

Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8196/Makefile.mk

@@ -34,6 +34,7 @@ romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 romstage-y += ../common/mt6363.c mt6363.c
 romstage-y += ../common/mt6373.c mt6373.c
+romstage-y += mtk_pwrsel.c
 romstage-y += ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif.c pmif_init.c
 romstage-y += pmif_spmi.c

src/soc/mediatek/mt8196/include/soc/addressmap.h

@@ -8,6 +8,7 @@ enum {
 	MCUPM_CFG_BASE		= 0x0C240000,
 	BUS_TRACE_MONITOR_BASE	= 0x0D040000,
 	IO_PHYS			= 0x10000000,
+	MFGSYS_BASE		= 0x40000000,
 };
 
 enum {

src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__
+#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__
+
+#include <soc/addressmap.h>
+
+#define VAL_PWRSEL			0x0
+#define VAL_PWRSEL_AUTO_MODE		0x1FF0000
+#define OFFSET_PWRSEL			0x04A0
+#define OFFSET_PWRSEL_AUTO_MODE_CFG	0x04A4
+
+#define MFG_VCORE_AO_CFG_BASE		(MFGSYS_BASE + 0x0B860000)		/* 0x4B860000 */
+#define MFG_VCORE_AO_RPC_PWRSEL_CONFIG	(MFG_VCORE_AO_CFG_BASE + 0x00B4)	/* 0x4B8600B4 */
+
+void pwrsel_init(void);
+
+#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */

src/soc/mediatek/mt8196/mtk_pwrsel.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/mtk_pwrsel.h>
+
+static void cpu_pwrsel_init(void)
+{
+	write32p(MCUSYS_BASE + OFFSET_PWRSEL, VAL_PWRSEL);
+	write32p(MCUSYS_BASE + OFFSET_PWRSEL_AUTO_MODE_CFG, VAL_PWRSEL_AUTO_MODE);
+}
+
+static void gpu_pwrsel_init(void)
+{
+	write32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG, GENMASK(14, 0));
+}
+
+void pwrsel_init(void)
+{
+	cpu_pwrsel_init();
+	gpu_pwrsel_init();
+
+	/* PWR_SEL must be 0x0 */
+	printk(BIOS_DEBUG, "PWR_SEL = %#x\n", read32p(MCUSYS_BASE + OFFSET_PWRSEL));
+	/* PWRSEL_CONFIG must be 0x7fff */
+	printk(BIOS_DEBUG, "PWRSEL_CONFIG = %#x\n", read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG));
+}