soc/mediatek/mt8196: Add PMIC MT6373 driver
1. Add MT6373 driver in soc folder 2 Add regulator API for powering on SD card 3. Add regulator API for VCN33_3 4. Add MT6373 LDO enable API TEST=build pass, check boot log with: [INFO ] mt6373_init_setting done [INFO ] pmic_protect_key_setting done BUG=b:317009620 Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Jarried Lin
Yu-Ping Wu
parent
bda5b83661
commit
8c6426c1b4
4 changed files with 711 additions and 0 deletions
79
src/soc/mediatek/common/include/soc/mt6373.h
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79
src/soc/mediatek/common/include/soc/mt6373.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT6373_H__
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#define __SOC_MEDIATEK_MT6373_H__
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#include <soc/spmi.h>
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#include <types.h>
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enum {
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MT6373_SWCID0 = 0xA,
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MT6373_SWCID1 = 0xB,
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MT6373_TOP_VRCTL_VOSEL_VBUCK0 = 0x24C,
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MT6373_TOP_VRCTL_VOSEL_VBUCK1 = 0x24D,
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MT6373_TOP_VRCTL_VOSEL_VBUCK2 = 0x24E,
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MT6373_BUCK_TOP_4PHASE_1_ANA_CON42 = 0x1A32,
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MT6373_BUCK_TOP_KEY_PROT_LO = 0x142A,
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MT6373_BUCK_TOP_KEY_PROT_HI = 0x142B,
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MT6373_BUCK_VBUCK0_DBG0 = 0x1496,
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MT6373_BUCK_VBUCK1_DBG0 = 0x1516,
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MT6373_BUCK_VBUCK2_DBG0 = 0x1596,
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MT6373_LDO_VCN33_3_CON0 = 0x1C23,
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MT6373_LDO_VCN33_3_CON1 = 0x1C24,
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MT6373_LDO_VANT18_CON0 = 0x1C87,
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MT6373_LDO_VANT18_CON1 = 0x1C88,
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MT6373_LDO_VMCH_CON0 = 0x1CB1,
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MT6373_LDO_VMC_CON0 = 0x1CC0,
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MT6373_LDO_VSIM1_CON0 = 0x1D31,
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MT6373_LDO_VSIM1_CON1 = 0x1D32,
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MT6373_LDO_VSIM2_CON0 = 0x1D40,
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MT6373_LDO_VSIM2_CON1 = 0x1D41,
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MT6373_VCN33_3_ANA_CON0 = 0x1E18,
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MT6373_VCN33_3_ANA_CON1 = 0x1E19,
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MT6373_VMCH_ANA_CON0 = 0x1E1C,
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MT6373_VMCH_ANA_CON1 = 0x1E1D,
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MT6373_VMC_ANA_CON0 = 0x1E24,
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MT6373_VMC_ANA_CON1 = 0x1E25,
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};
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struct mt6373_setting {
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unsigned short addr;
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unsigned short val;
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unsigned short mask;
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unsigned char shift;
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};
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struct mt6373_efuse {
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unsigned short efuse_bit;
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unsigned short addr;
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unsigned short mask;
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unsigned char shift;
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};
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enum {
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MT6373_VBUCK0 = 0,
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MT6373_VBUCK1,
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MT6373_VBUCK2,
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MT6373_VMC,
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MT6373_VMCH,
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MT6373_MAX,
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};
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void mt6373_init(void);
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void mt6373_set_vmc_voltage(u32 vmc_uv);
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u32 mt6373_get_vmc_voltage(void);
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void mt6373_set_vmch_voltage(u32 vmch_uv);
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u32 mt6373_get_vmch_voltage(void);
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void mt6373_set_vcn33_3_voltage(u32 vcn33_3_uv);
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void mt6373_enable_vcn33_3(bool enable);
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void mt6373_enable_vmc(bool enable);
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void mt6373_enable_vmch(bool enable);
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void mt6373_enable_vant18(bool enable);
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void mt6373_enable_vsim1(bool enable);
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void mt6373_enable_vsim2(bool enable);
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void mt6373_init_pmif_arb(void);
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void mt6373_write_field(u32 reg, u32 val, u32 mask, u32 shift);
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void mt6373_init_setting(void);
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void mt6373_lp_setting(void);
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#endif /* __SOC_MEDIATEK_MT6373_H__ */
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264
src/soc/mediatek/common/mt6373.c
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264
src/soc/mediatek/common/mt6373.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/mt6373.h>
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#include <soc/pmif.h>
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#include <timer.h>
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static const struct mt6373_setting key_protect_setting[] = {
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{0x39E, 0x8C, 0xFF, 0},
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{0x39F, 0x9C, 0xFF, 0},
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{0xFAB, 0x73, 0xFF, 0},
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{0xFAC, 0x63, 0xFF, 0},
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{0x142A, 0x43, 0xFF, 0},
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{0x142B, 0x55, 0xFF, 0},
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{0x3A7, 0x8C, 0xFF, 0},
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{0x3A8, 0x9C, 0xFF, 0},
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{0xA1A, 0x29, 0xFF, 0},
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{0xA1B, 0x47, 0xFF, 0},
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};
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static struct pmif *pmif_arb;
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static void mt6373_write8(u32 reg, u8 data)
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{
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assert(pmif_arb);
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pmif_arb->write(pmif_arb, SPMI_SLAVE_5, reg, data);
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}
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static u32 mt6373_read_field(u32 reg, u32 mask, u32 shift)
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{
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assert(pmif_arb);
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return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_5, reg, mask, shift);
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}
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void mt6373_write_field(u32 reg, u32 val, u32 mask, u32 shift)
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{
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assert(pmif_arb);
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pmif_arb->write_field(pmif_arb, SPMI_SLAVE_5, reg, val, mask, shift);
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}
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static void pmic_protect_key_setting(bool lock)
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{
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for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++)
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mt6373_write8(key_protect_setting[i].addr,
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lock ? 0 : key_protect_setting[i].val);
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printk(BIOS_INFO, "%s done\n", __func__);
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}
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void mt6373_set_vmc_voltage(u32 vmc_uv)
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{
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u32 reg_vol, reg_cali;
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assert(pmif_arb);
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if (vmc_uv >= 1200000 && vmc_uv <= 1300000)
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reg_vol = (vmc_uv - 1200000) / 100000;
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else if (vmc_uv >= 1500000 && vmc_uv <= 1700000)
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reg_vol = (vmc_uv - 1500000) / 200000 + 2;
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else if (vmc_uv >= 1800000 && vmc_uv <= 2000000)
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reg_vol = (vmc_uv - 1800000) / 200000 + 4;
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else if (vmc_uv >= 2100000 && vmc_uv <= 2200000)
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reg_vol = (vmc_uv - 2100000) / 100000 + 6;
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else if (vmc_uv >= 2700000 && vmc_uv <= 3100000)
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reg_vol = (vmc_uv - 2700000) / 100000 + 8;
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else if (vmc_uv >= 3300000 && vmc_uv <= 3500000)
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reg_vol = (vmc_uv - 3300000) / 100000 + 13;
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else
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die("ERROR: Unknown vmc voltage %u", vmc_uv);
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reg_cali = ((vmc_uv / 1000) % 100) / 10;
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mt6373_write8(MT6373_VMC_ANA_CON1, reg_vol);
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mt6373_write8(MT6373_VMC_ANA_CON0, reg_cali);
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printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmc_uv);
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}
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u32 mt6373_get_vmc_voltage(void)
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{
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u32 reg_vol, reg_cali, vol;
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assert(pmif_arb);
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reg_vol = mt6373_read_field(MT6373_VMC_ANA_CON1, 0xF, 0);
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reg_cali = mt6373_read_field(MT6373_VMC_ANA_CON0, 0xF, 0);
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if (reg_vol == 0 || reg_vol == 1)
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vol = (reg_vol - 0) * 100000 + 1200000;
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else if (reg_vol == 2 || reg_vol == 3)
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vol = (reg_vol - 2) * 200000 + 1500000;
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else if (reg_vol == 4 || reg_vol == 5)
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vol = (reg_vol - 4) * 200000 + 1800000;
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else if (reg_vol == 6 || reg_vol == 7)
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vol = (reg_vol - 6) * 100000 + 2100000;
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else if (reg_vol >= 8 && reg_vol <= 12)
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vol = (reg_vol - 8) * 100000 + 2700000;
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else if (reg_vol >= 13 && reg_vol <= 15)
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vol = (reg_vol - 13) * 100000 + 3300000;
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else
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die("ERROR: Unknown vsim1 reg_vol %x", reg_vol);
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printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n",
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__func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000));
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return (vol + reg_cali * 1000);
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}
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void mt6373_set_vmch_voltage(u32 vmch_uv)
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{
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u32 reg_vol, reg_cali;
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assert(pmif_arb);
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if (vmch_uv >= 1200000 && vmch_uv <= 1300000)
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reg_vol = (vmch_uv - 1200000) / 100000;
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else if (vmch_uv >= 1500000 && vmch_uv <= 1700000)
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reg_vol = (vmch_uv - 1500000) / 200000 + 2;
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else if (vmch_uv >= 1800000 && vmch_uv <= 2000000)
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reg_vol = (vmch_uv - 1800000) / 200000 + 4;
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else if (vmch_uv >= 2500000 && vmch_uv <= 3100000)
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reg_vol = (vmch_uv - 2500000) / 100000 + 6;
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else if (vmch_uv >= 3300000 && vmch_uv <= 3500000)
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reg_vol = (vmch_uv - 3300000) / 100000 + 13;
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else
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die("ERROR: Unknown vmc voltage %u", vmch_uv);
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reg_cali = ((vmch_uv / 1000) % 100) / 10;
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mt6373_write8(MT6373_VMCH_ANA_CON1, reg_vol);
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mt6373_write8(MT6373_VMCH_ANA_CON0, reg_cali);
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printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmch_uv);
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}
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u32 mt6373_get_vmch_voltage(void)
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{
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u32 reg_vol, reg_cali, vol;
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assert(pmif_arb);
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reg_vol = mt6373_read_field(MT6373_VMCH_ANA_CON1, 0xF, 0);
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reg_cali = mt6373_read_field(MT6373_VMCH_ANA_CON0, 0xF, 0);
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if (reg_vol == 0 || reg_vol == 1)
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vol = (reg_vol - 0) * 100000 + 1200000;
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else if (reg_vol == 2 || reg_vol == 3)
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vol = (reg_vol - 2) * 200000 + 1500000;
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else if (reg_vol == 4 || reg_vol == 5)
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vol = (reg_vol - 4) * 200000 + 1800000;
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else if (reg_vol >= 6 && reg_vol <= 12)
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vol = (reg_vol - 6) * 100000 + 2500000;
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else if (reg_vol >= 13 && reg_vol <= 15)
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vol = (reg_vol - 13) * 100000 + 3300000;
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else
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die("ERROR: Unknown vsim1 reg_vol %x", reg_vol);
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printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n",
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__func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000));
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return (vol + reg_cali * 1000);
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}
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void mt6373_set_vcn33_3_voltage(u32 vcn33_3_uv)
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{
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udelay(100);
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printk(BIOS_INFO, "%s start\n", __func__);
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u32 reg_vol, reg_cali;
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assert(pmif_arb);
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if (vcn33_3_uv >= 1200000 && vcn33_3_uv <= 1300000)
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reg_vol = (vcn33_3_uv - 1200000) / 100000;
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else if (vcn33_3_uv >= 1500000 && vcn33_3_uv <= 1700000)
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reg_vol = (vcn33_3_uv - 1500000) / 200000 + 2;
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else if (vcn33_3_uv >= 1800000 && vcn33_3_uv <= 2000000)
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reg_vol = (vcn33_3_uv - 1800000) / 200000 + 4;
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else if (vcn33_3_uv >= 2500000 && vcn33_3_uv <= 3100000)
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reg_vol = (vcn33_3_uv - 2500000) / 100000 + 6;
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else if (vcn33_3_uv >= 3300000 && vcn33_3_uv <= 3500000)
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reg_vol = (vcn33_3_uv - 3300000) / 100000 + 13;
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else
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die("ERROR: Unknown vcn33_3_uv voltage %u", vcn33_3_uv);
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reg_cali = ((vcn33_3_uv / 1000) % 100) / 10;
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mt6373_write8(MT6373_VCN33_3_ANA_CON1, reg_vol);
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udelay(100);
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mt6373_write8(MT6373_VCN33_3_ANA_CON0, reg_cali);
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udelay(100);
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printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vcn33_3_uv);
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}
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void mt6373_enable_vcn33_3(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VCN33_3_CON0, enable, 0x1, 0);
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}
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void mt6373_enable_vmc(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VMC_CON0, enable, 0x1, 0);
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}
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void mt6373_enable_vmch(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VMCH_CON0, enable, 0x1, 0);
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}
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void mt6373_enable_vant18(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VANT18_CON0, enable, 0x1, 0);
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}
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void mt6373_enable_vsim1(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VSIM1_CON0, enable, 0x1, 0);
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}
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void mt6373_enable_vsim2(bool enable)
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{
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mt6373_write_field(MT6373_LDO_VSIM2_CON0, enable, 0x1, 0);
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}
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static void mt6373_pmic_wdt_set(void)
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{
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/* [5]=1, RG_WDTRSTB_DEB */
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mt6373_write_field(0x13a, 0x20, 0xFF, 0);
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/* [1]=0, RG_WDTRSTB_MODE */
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mt6373_write_field(0x13b, 0x02, 0xFF, 0);
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/* [0]=1, RG_WDTRSTB_EN */
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mt6373_write_field(0x13a, 0x01, 0xFF, 0);
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/* Enable BUCK/LDO WDT VOSEL Debug */
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mt6373_write_field(0x231, 0x1, 0x1, 0);
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/* Clear WDT status */
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mt6373_write_field(0x13a, 0x1, 0x1, 3);
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udelay(50);
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mt6373_write_field(0x13b, 0x1, 0x1, 3);
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printk(BIOS_INFO, "[%s]WDTRSTB[0x139]=0x%x\n", __func__,
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mt6373_read_field(0x139, 0xFF, 0));
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}
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void mt6373_init_pmif_arb(void)
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{
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if (!pmif_arb) {
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pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1);
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assert(pmif_arb);
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}
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if (pmif_arb->is_pmif_init_done(pmif_arb))
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die("%s: initialization failed", __func__);
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printk(BIOS_INFO, "[%s][MT6373]CHIP ID = 0x%x\n",
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__func__, mt6373_read_field(MT6373_SWCID1, 0xFF, 0));
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}
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void mt6373_init(void)
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{
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printk(BIOS_INFO, "%s start\n", __func__);
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mt6373_init_pmif_arb();
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mt6373_pmic_wdt_set();
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pmic_protect_key_setting(false);
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mt6373_init_setting();
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pmic_protect_key_setting(true);
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}
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@ -31,6 +31,7 @@ romstage-y += ../common/memory.c memory.c
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romstage-y += ../common/memory_test.c
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romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
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romstage-y += ../common/mt6363.c mt6363.c
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romstage-y += ../common/mt6373.c mt6373.c
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romstage-y += ../common/pmif_clk.c pmif_clk.c
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romstage-y += ../common/pmif.c pmif_init.c
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romstage-y += pmif_spmi.c
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@ -46,6 +47,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
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ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c
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ramstage-y += ../common/mt6363.c mt6363.c
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ramstage-y += ../common/mt6363_sdmadc.c
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ramstage-y += ../common/mt6373.c mt6373.c
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ramstage-y += soc.c
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ramstage-y += ../common/sspm.c sspm_sram.c
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ramstage-y += ../common/pmif_clk.c pmif_clk.c
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366
src/soc/mediatek/mt8196/mt6373.c
Normal file
366
src/soc/mediatek/mt8196/mt6373.c
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* These values are used by MediaTek internally.
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* We can find these registers in "MT6373TP_PMIC_Design_Notice_for_MT8196G_V0.2".
|
||||
* The setting values are provided by MeidaTek designers.
|
||||
*/
|
||||
|
||||
#include <soc/mt6373.h>
|
||||
#include <console/console.h>
|
||||
|
||||
static const struct mt6373_setting init_setting[] = {
|
||||
/* For VIO18 switch to DIG18 feature */
|
||||
{0xA95, 0x1, 0x1, 7},
|
||||
{0x16, 0xA, 0xA, 0},
|
||||
{0x19, 0x1F, 0x1F, 0},
|
||||
{0x21, 0x1, 0x1, 0},
|
||||
{0x22, 0x61, 0x61, 0},
|
||||
{0x4C, 0x0, 0xFF, 0},
|
||||
{0x4F, 0x0, 0x80, 0},
|
||||
{0x5A, 0x5, 0x5, 0},
|
||||
{0x91, 0x93, 0xFF, 0},
|
||||
{0x94, 0xFF, 0xFF, 0},
|
||||
{0x97, 0xF, 0xFF, 0},
|
||||
{0xC4, 0x0, 0x38, 0},
|
||||
{0xC7, 0x0, 0x3F, 0},
|
||||
{0xCA, 0x0, 0x3F, 0},
|
||||
{0xCD, 0x0, 0x3F, 0},
|
||||
{0xD0, 0x0, 0x3F, 0},
|
||||
{0xD3, 0x0, 0x3F, 0},
|
||||
{0xD6, 0x0, 0x3F, 0},
|
||||
{0x10F, 0x10, 0x10, 0},
|
||||
{0x112, 0x4, 0x4, 0},
|
||||
{0x12D, 0x1, 0x1, 0},
|
||||
{0x139, 0x21, 0x21, 0},
|
||||
{0x230, 0x0, 0x1, 0},
|
||||
{0x3A6, 0x3, 0x3, 0},
|
||||
{0x413, 0x7, 0xFF, 0},
|
||||
{0x416, 0x12, 0xFF, 0},
|
||||
{0x417, 0x0, 0x7, 0},
|
||||
{0x90D, 0x10, 0x10, 0},
|
||||
{0xA17, 0xFF, 0xFF, 0},
|
||||
{0xA18, 0xFF, 0xFF, 0},
|
||||
{0xA19, 0xFC, 0xFC, 0},
|
||||
{0xA1D, 0xE, 0xFF, 0},
|
||||
{0xA1E, 0x7, 0xFF, 0},
|
||||
{0xA1F, 0x0, 0xFF, 0},
|
||||
{0xA20, 0xFF, 0xFF, 0},
|
||||
{0xA21, 0xE, 0xFF, 0},
|
||||
{0xA22, 0xFF, 0xFF, 0},
|
||||
{0xA23, 0xFF, 0xFF, 0},
|
||||
{0xA24, 0xC, 0xFF, 0},
|
||||
{0xA25, 0xB, 0xFF, 0},
|
||||
{0xA26, 0xA, 0xFF, 0},
|
||||
{0xA27, 0x7, 0xFF, 0},
|
||||
{0xA28, 0x7, 0xFF, 0},
|
||||
{0xA29, 0x7, 0xFF, 0},
|
||||
{0xA2A, 0x5, 0xFF, 0},
|
||||
{0xA2B, 0xFF, 0xFF, 0},
|
||||
{0xA2C, 0xFF, 0xFF, 0},
|
||||
{0xA2D, 0xFF, 0xFF, 0},
|
||||
{0xA2E, 0xFF, 0xFF, 0},
|
||||
{0xA2F, 0xFF, 0xFF, 0},
|
||||
{0xA30, 0xFF, 0xFF, 0},
|
||||
{0xA31, 0xFF, 0xFF, 0},
|
||||
{0xA32, 0xFF, 0xFF, 0},
|
||||
{0xA33, 0xFF, 0xFF, 0},
|
||||
{0xF8C, 0x15, 0x15, 0},
|
||||
{0xF8D, 0x25, 0x25, 0},
|
||||
{0x1188, 0x0, 0x80, 0},
|
||||
{0x1190, 0x13, 0xFF, 0},
|
||||
{0x119B, 0x20, 0xFF, 0},
|
||||
{0x119D, 0x60, 0x70, 0},
|
||||
{0x11A0, 0x60, 0x70, 0},
|
||||
{0x11C6, 0xF, 0xF, 0},
|
||||
{0x11C7, 0x0, 0xF, 0},
|
||||
{0x140E, 0x0, 0x40, 0},
|
||||
{0x144A, 0x0, 0xFF, 0},
|
||||
{0x144B, 0x0, 0xFF, 0},
|
||||
{0x144C, 0x0, 0xF, 0},
|
||||
{0x1487, 0x40, 0xFF, 0},
|
||||
{0x1488, 0x0, 0x1, 0},
|
||||
{0x148A, 0x5, 0x7F, 0},
|
||||
{0x1507, 0x40, 0xFF, 0},
|
||||
{0x1508, 0x0, 0x1, 0},
|
||||
{0x150A, 0x5, 0x7F, 0},
|
||||
{0x1587, 0x40, 0xFF, 0},
|
||||
{0x1588, 0x0, 0x1, 0},
|
||||
{0x158A, 0x5, 0x7F, 0},
|
||||
{0x1607, 0x40, 0xFF, 0},
|
||||
{0x1608, 0x0, 0x1, 0},
|
||||
{0x160A, 0x5, 0x7F, 0},
|
||||
{0x1687, 0x40, 0xFF, 0},
|
||||
{0x1688, 0x0, 0x1, 0},
|
||||
{0x168B, 0xC, 0x7F, 0},
|
||||
{0x1707, 0x40, 0xFF, 0},
|
||||
{0x1708, 0x0, 0x1, 0},
|
||||
{0x170B, 0xC, 0x7F, 0},
|
||||
{0x1787, 0x92, 0xFF, 0},
|
||||
{0x1788, 0x0, 0x1, 0},
|
||||
{0x1807, 0x40, 0xFF, 0},
|
||||
{0x1808, 0x0, 0x1, 0},
|
||||
{0x180A, 0x5, 0x7F, 0},
|
||||
{0x1887, 0x6C, 0xFF, 0},
|
||||
{0x1888, 0x0, 0x1, 0},
|
||||
{0x188A, 0x19, 0x7F, 0},
|
||||
{0x188B, 0x33, 0x7F, 0},
|
||||
{0x1907, 0x98, 0xFF, 0},
|
||||
{0x1908, 0x0, 0x1, 0},
|
||||
{0x190A, 0x19, 0x7F, 0},
|
||||
{0x190B, 0x33, 0x7F, 0},
|
||||
{0x198A, 0x2E, 0x2F, 0},
|
||||
{0x198C, 0xF8, 0xF8, 0},
|
||||
{0x198D, 0x32, 0x3F, 0},
|
||||
{0x198F, 0xC, 0xC, 0},
|
||||
{0x1990, 0xED, 0xFF, 0},
|
||||
{0x1991, 0x10, 0xFF, 0},
|
||||
{0x1994, 0x2E, 0x2F, 0},
|
||||
{0x1996, 0xF8, 0xF8, 0},
|
||||
{0x1997, 0x32, 0x3F, 0},
|
||||
{0x1999, 0xC, 0xC, 0},
|
||||
{0x199A, 0xED, 0xFF, 0},
|
||||
{0x199B, 0x10, 0xFF, 0},
|
||||
{0x19A0, 0xF, 0xF, 0},
|
||||
{0x19A1, 0x45, 0xFF, 0},
|
||||
{0x19A2, 0x45, 0xFF, 0},
|
||||
{0x19A3, 0xC, 0xC, 0},
|
||||
{0x19B5, 0x5, 0x87, 0},
|
||||
{0x19BD, 0x85, 0x87, 0},
|
||||
{0x19C0, 0x0, 0x18, 0},
|
||||
{0x1A08, 0x10, 0x10, 0},
|
||||
{0x1A09, 0x2D, 0x2F, 0},
|
||||
{0x1A0A, 0xC1, 0xC1, 0},
|
||||
{0x1A0B, 0xFA, 0xFF, 0},
|
||||
{0x1A0C, 0x32, 0x3F, 0},
|
||||
{0x1A0E, 0xC, 0xC, 0},
|
||||
{0x1A0F, 0x77, 0xFF, 0},
|
||||
{0x1A10, 0xC0, 0xFF, 0},
|
||||
{0x1A11, 0x6B, 0x7F, 0},
|
||||
{0x1A12, 0x10, 0x10, 0},
|
||||
{0x1A13, 0x2D, 0x2F, 0},
|
||||
{0x1A14, 0xC1, 0xC1, 0},
|
||||
{0x1A15, 0xFA, 0xFF, 0},
|
||||
{0x1A16, 0x32, 0x3F, 0},
|
||||
{0x1A18, 0xC, 0xC, 0},
|
||||
{0x1A19, 0x77, 0xFF, 0},
|
||||
{0x1A1A, 0xC0, 0xFF, 0},
|
||||
{0x1A1B, 0x6B, 0x7F, 0},
|
||||
{0x1A1C, 0x10, 0x10, 0},
|
||||
{0x1A1D, 0x2D, 0x2F, 0},
|
||||
{0x1A1E, 0xC1, 0xC1, 0},
|
||||
{0x1A1F, 0xFA, 0xFF, 0},
|
||||
{0x1A20, 0x32, 0x3F, 0},
|
||||
{0x1A22, 0xC, 0xC, 0},
|
||||
{0x1A23, 0x77, 0xFF, 0},
|
||||
{0x1A24, 0xC0, 0xFF, 0},
|
||||
{0x1A25, 0x6B, 0x7F, 0},
|
||||
{0x1A26, 0x10, 0x10, 0},
|
||||
{0x1A27, 0x2D, 0x2F, 0},
|
||||
{0x1A28, 0xC1, 0xC1, 0},
|
||||
{0x1A29, 0xFA, 0xFF, 0},
|
||||
{0x1A2A, 0x32, 0x3F, 0},
|
||||
{0x1A2C, 0xC, 0xC, 0},
|
||||
{0x1A2D, 0x77, 0xFF, 0},
|
||||
{0x1A2E, 0xC0, 0xFF, 0},
|
||||
{0x1A2F, 0x6B, 0x7F, 0},
|
||||
{0x1A37, 0xFF, 0xFF, 0},
|
||||
{0x1A39, 0x5F, 0xFF, 0},
|
||||
{0x1A3A, 0x5F, 0xFF, 0},
|
||||
{0x1A3B, 0x5F, 0xFF, 0},
|
||||
{0x1A3C, 0x5F, 0xFF, 0},
|
||||
{0x1A3D, 0xF0, 0xF0, 0},
|
||||
{0x1A46, 0x6, 0x87, 0},
|
||||
{0x1A4E, 0x6, 0x87, 0},
|
||||
{0x1A56, 0x6, 0x87, 0},
|
||||
{0x1A5E, 0x6, 0x87, 0},
|
||||
{0x1A61, 0x0, 0x78, 0},
|
||||
{0x1A88, 0x10, 0x50, 0},
|
||||
{0x1A89, 0x2D, 0x2F, 0},
|
||||
{0x1A8B, 0xF8, 0xF8, 0},
|
||||
{0x1A8C, 0x32, 0x3F, 0},
|
||||
{0x1A8E, 0xC, 0xC, 0},
|
||||
{0x1A8F, 0xED, 0xFF, 0},
|
||||
{0x1A90, 0x0, 0xFF, 0},
|
||||
{0x1A92, 0x10, 0x10, 0},
|
||||
{0x1A93, 0x2D, 0x2F, 0},
|
||||
{0x1A95, 0xF8, 0xF8, 0},
|
||||
{0x1A96, 0x32, 0x3F, 0},
|
||||
{0x1A98, 0xC, 0xC, 0},
|
||||
{0x1A99, 0xED, 0xFF, 0},
|
||||
{0x1A9C, 0x10, 0x16, 0},
|
||||
{0x1A9D, 0x2D, 0x2F, 0},
|
||||
{0x1A9F, 0xF8, 0xF8, 0},
|
||||
{0x1AA0, 0x32, 0x3F, 0},
|
||||
{0x1AA2, 0xC, 0xC, 0},
|
||||
{0x1AA3, 0xED, 0xFF, 0},
|
||||
{0x1AA4, 0x0, 0xFF, 0},
|
||||
{0x1AA6, 0x10, 0x56, 0},
|
||||
{0x1AA7, 0x2D, 0x2F, 0},
|
||||
{0x1AA9, 0xF8, 0xF8, 0},
|
||||
{0x1AAA, 0x32, 0x3F, 0},
|
||||
{0x1AAC, 0xC, 0xC, 0},
|
||||
{0x1AAD, 0xED, 0xFF, 0},
|
||||
{0x1AB6, 0x20, 0x30, 0},
|
||||
{0x1AB7, 0xF0, 0xF0, 0},
|
||||
{0x1AB9, 0xCD, 0xFF, 0},
|
||||
{0x1ABA, 0xCD, 0xFF, 0},
|
||||
{0x1ABB, 0xE5, 0xFF, 0},
|
||||
{0x1ABC, 0xCD, 0xFF, 0},
|
||||
{0x1ABD, 0xF0, 0xF0, 0},
|
||||
{0x1AC6, 0x6, 0x87, 0},
|
||||
{0x1ACE, 0x86, 0x87, 0},
|
||||
{0x1AD6, 0x6, 0x87, 0},
|
||||
{0x1ADE, 0x6, 0x87, 0},
|
||||
{0x1AE1, 0x28, 0x78, 0},
|
||||
{0x1B0D, 0xF, 0xF, 0},
|
||||
{0x1B0E, 0x1, 0x1, 0},
|
||||
{0x1B10, 0xFF, 0xFF, 0},
|
||||
{0x1B13, 0xFF, 0xFF, 0},
|
||||
{0x1B16, 0xFF, 0xFF, 0},
|
||||
{0x1B2A, 0x8, 0x8, 0},
|
||||
{0x1B88, 0x10, 0x10, 0},
|
||||
{0x1B89, 0x0, 0x80, 0},
|
||||
{0x1B96, 0x10, 0x10, 0},
|
||||
{0x1B97, 0x0, 0x80, 0},
|
||||
{0x1BA4, 0x10, 0x10, 0},
|
||||
{0x1BA5, 0x0, 0x80, 0},
|
||||
{0x1BAA, 0x40, 0x40, 0},
|
||||
{0x1BB2, 0x10, 0x10, 0},
|
||||
{0x1BB3, 0x0, 0x80, 0},
|
||||
{0x1BC0, 0x10, 0x10, 0},
|
||||
{0x1BC1, 0x0, 0x80, 0},
|
||||
{0x1BCE, 0x10, 0x10, 0},
|
||||
{0x1BCF, 0x0, 0x80, 0},
|
||||
{0x1C08, 0x10, 0x10, 0},
|
||||
{0x1C09, 0x0, 0x80, 0},
|
||||
{0x1C16, 0x10, 0x10, 0},
|
||||
{0x1C17, 0x0, 0x80, 0},
|
||||
{0x1C24, 0x10, 0x10, 0},
|
||||
{0x1C25, 0x0, 0x80, 0},
|
||||
{0x1C32, 0x10, 0x10, 0},
|
||||
{0x1C33, 0x0, 0x80, 0},
|
||||
{0x1C40, 0x10, 0x10, 0},
|
||||
{0x1C41, 0x0, 0x80, 0},
|
||||
{0x1C4E, 0x10, 0x10, 0},
|
||||
{0x1C4F, 0x0, 0x80, 0},
|
||||
{0x1C88, 0x10, 0x10, 0},
|
||||
{0x1C89, 0x0, 0x80, 0},
|
||||
{0x1C96, 0x10, 0x10, 0},
|
||||
{0x1C97, 0x0, 0x80, 0},
|
||||
{0x1CA4, 0x10, 0x10, 0},
|
||||
{0x1CA5, 0x0, 0x80, 0},
|
||||
{0x1CB2, 0x10, 0x10, 0},
|
||||
{0x1CB3, 0x0, 0x80, 0},
|
||||
{0x1CC1, 0x10, 0x10, 0},
|
||||
{0x1CC2, 0x0, 0x80, 0},
|
||||
{0x1CCF, 0x10, 0x10, 0},
|
||||
{0x1CD0, 0x0, 0x80, 0},
|
||||
{0x1D08, 0x30, 0x30, 0},
|
||||
{0x1D09, 0x0, 0x80, 0},
|
||||
{0x1D16, 0x30, 0x30, 0},
|
||||
{0x1D17, 0x0, 0x80, 0},
|
||||
{0x1D24, 0x30, 0x30, 0},
|
||||
{0x1D25, 0x0, 0x80, 0},
|
||||
{0x1D32, 0x30, 0x30, 0},
|
||||
{0x1D33, 0x0, 0x80, 0},
|
||||
{0x1D41, 0x30, 0x30, 0},
|
||||
{0x1D42, 0x0, 0x80, 0},
|
||||
{0x1D88, 0x10, 0x10, 0},
|
||||
{0x1D89, 0x0, 0x80, 0},
|
||||
{0x1D91, 0xC, 0x7F, 0},
|
||||
{0x1D92, 0xC, 0x7F, 0},
|
||||
{0x1E0C, 0x0, 0xF, 0},
|
||||
{0x1E22, 0x1, 0x1, 0},
|
||||
{0x1E3A, 0x1, 0x1, 0},
|
||||
{0x1E3E, 0x1, 0x1, 0},
|
||||
{0x1E97, 0x2, 0x3, 0},
|
||||
{0x1E9B, 0x2, 0x3, 0},
|
||||
{0x1F0B, 0x8, 0xC, 0},
|
||||
{0x1F0F, 0x8, 0xC, 0},
|
||||
{0x1F8B, 0x8, 0xC, 0},
|
||||
{0x1F8F, 0x20, 0x30, 0},
|
||||
|
||||
/* Add UVLO 2.0 setting. also need to modify dts setting for main pmic */
|
||||
{0xA36, 0x2, 0x2, 0},
|
||||
{0xA89, 0x5, 0xF, 0},
|
||||
{0xA8A, 0x3, 0xF, 0},
|
||||
{0xA95, 0x40, 0x40, 0},
|
||||
};
|
||||
|
||||
static const struct mt6373_setting lp_setting[] = {
|
||||
/* Suspend */
|
||||
{0x14a0, 0x1, 0x1, 0x0},
|
||||
{0x1494, 0x1, 0x1, 0x0},
|
||||
{0x149a, 0x1, 0x1, 0x0},
|
||||
{0x15a0, 0x1, 0x1, 0x0},
|
||||
{0x1594, 0x1, 0x1, 0x0},
|
||||
{0x159a, 0x1, 0x1, 0x0},
|
||||
{0x1820, 0x1, 0x1, 0x0},
|
||||
{0x1814, 0x1, 0x1, 0x0},
|
||||
{0x181a, 0x1, 0x1, 0x0},
|
||||
{0x18a0, 0x1, 0x1, 0x0},
|
||||
{0x1894, 0x1, 0x1, 0x0},
|
||||
{0x189a, 0x1, 0x1, 0x0},
|
||||
{0x1cac, 0x1, 0x1, 0xa},
|
||||
{0x1cb2, 0x1, 0x1, 0x0},
|
||||
{0x1cb8, 0x1, 0x1, 0x0},
|
||||
{0x1bbe, 0x1, 0x1, 0xa},
|
||||
{0x1bc4, 0x1, 0x1, 0x0},
|
||||
{0x1bca, 0x1, 0x1, 0x0},
|
||||
{0x1d22, 0x1, 0x1, 0xe},
|
||||
{0x1d28, 0x0, 0x1, 0xe},
|
||||
{0x1c64, 0x1, 0x1, 0xa},
|
||||
{0x1c6a, 0x1, 0x1, 0x0},
|
||||
{0x1c70, 0x1, 0x1, 0x0},
|
||||
{0x1d34, 0x1, 0x1, 0xe},
|
||||
{0x1d3a, 0x0, 0x1, 0xe},
|
||||
{0x1c88, 0x1, 0x1, 0xa},
|
||||
{0x1c8e, 0x1, 0x1, 0x0},
|
||||
{0x1c94, 0x1, 0x1, 0x0},
|
||||
{0x1b9a, 0x1, 0x1, 0xa},
|
||||
{0x1ba0, 0x1, 0x1, 0x0},
|
||||
{0x1ba6, 0x1, 0x1, 0x0},
|
||||
{0x1d08, 0x1, 0x1, 0xa},
|
||||
{0x1d0e, 0x1, 0x1, 0x0},
|
||||
{0x1d14, 0x1, 0x1, 0x0},
|
||||
{0x1d0e, 0x1, 0x1, 0x0},
|
||||
{0x1d14, 0x1, 0x1, 0x0},
|
||||
{0x1d9a, 0x1, 0x1, 0xa},
|
||||
{0x1da0, 0x1, 0x1, 0x0},
|
||||
{0x1da6, 0x1, 0x1, 0x0},
|
||||
|
||||
/* Deep idle */
|
||||
{0x1bbe, 0x1, 0x1, 0xc},
|
||||
{0x1bc4, 0x1, 0x1, 0x2},
|
||||
{0x1bca, 0x1, 0x1, 0x2},
|
||||
{0x1c64, 0x1, 0x1, 0xc},
|
||||
{0x1c6a, 0x1, 0x1, 0x2},
|
||||
{0x1c70, 0x1, 0x1, 0x2},
|
||||
{0x1c88, 0x1, 0x1, 0xc},
|
||||
{0x1c8e, 0x1, 0x1, 0x2},
|
||||
{0x1c94, 0x1, 0x1, 0x2},
|
||||
{0x1b9a, 0x1, 0x1, 0xc},
|
||||
{0x1ba0, 0x1, 0x1, 0x2},
|
||||
{0x1ba6, 0x1, 0x1, 0x2},
|
||||
{0x1d08, 0x1, 0x1, 0xc},
|
||||
{0x1d0e, 0x1, 0x1, 0x2},
|
||||
{0x1d14, 0x1, 0x1, 0x2},
|
||||
{0x1d0e, 0x1, 0x1, 0x2},
|
||||
{0x1d14, 0x1, 0x1, 0x2},
|
||||
};
|
||||
|
||||
void mt6373_init_setting(void)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(init_setting); i++)
|
||||
mt6373_write_field(init_setting[i].addr, init_setting[i].val,
|
||||
init_setting[i].mask, init_setting[i].shift);
|
||||
printk(BIOS_INFO, "%s done\n", __func__);
|
||||
}
|
||||
|
||||
void mt6373_lp_setting(void)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(lp_setting); i++)
|
||||
mt6373_write_field(lp_setting[i].addr, lp_setting[i].val,
|
||||
lp_setting[i].mask, lp_setting[i].shift);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue