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soc/intel: Log CSE Sync Early Sign of Life event from a better place

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CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.

BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.

Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2024-11-12 11:45:38 -07:00 • committed by Subrata Banik
commit 9a15a1ed21
4 changed files with 10 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -439,13 +439,15 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
* packed as part of the CBFS then CSE sync will be triggered. CSE sync can take
* < 1-minute hence, let's inform the end user with an on-screen text message.
*/
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
&& !is_cse_boot_to_rw()) {
if (esol_required) {
name = "memory training and CSE update";
} else {
name = "CSE update";
esol_required = true;
}
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
}
if (esol_required)

4
src/soc/intel/alderlake/romstage/romstage.c
View file

@ -208,8 +208,10 @@ void mainboard_romstage_entry(void)
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
cse_fill_bp_info();
if (CONFIG(CHROMEOS_ENABLE_ESOL) &&
is_cse_fw_update_required() && !is_cse_boot_to_rw())
is_cse_fw_update_required() && !is_cse_boot_to_rw()) {
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
ux_inform_user_of_update_operation("CSE update");
}
cse_fw_sync();
}

1
src/soc/intel/common/block/cse/cse_lite.c
View file

@ -806,7 +806,6 @@ static enum cb_err cse_write_rw_region(const struct region_device *target_rdev,
return CB_ERR;
printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n");
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
return CB_SUCCESS;
}

5
src/soc/intel/meteorlake/romstage/fsp_params.c
View file

@ -456,8 +456,11 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
}
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required())
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
&& !is_cse_boot_to_rw()) {
vga_init_control = VGA_INIT_CONTROL_ENABLE;
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
}
if (!vga_init_control)
return;