erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/common/cnvi: Fix GBTE path in comment

Browse source 
Change-Id: If1e5d70a23c2a139ef3ee4970db2e5d528c2661e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84991
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2024-10-24 14:21:55 +01:00 • committed by Lean Sheng Tan
commit 0bb4a220a8
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/common/block/cnvi/cnvi.c
View file

@ -129,7 +129,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
* If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero))
* {
* Local2 = Zero
* If ((GBTE() == One))
* If ((\_SB.PCI0.GBTE() == One))
* {
* \_SB.PCI0.BTRK (Zero)
* Sleep (105)