soc/mediatek/mt8196: Add booker driver

The MediaTek booker (the customized ARM CI-700) is a high-performance
interconnect architecture designed for multi-core processor systems,
providing high bandwidth, low latency data transfer. And booker mainly
uses CHI protocol, but doesn't support coherence (which is achieved
through ACP solution). Additionally, the booker also uses other
protocols such as AXI, which translates CHI transactions into EMI's AXI
transactions.

Currently, the mt8196 booker only uses the functions of SLC CMO routing.
If downstream SLC needs CMO command propagation from the DSU, it is
needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of
each SBSX node in order to propagate the CMO command.

Increase the bootblock size from 75K to 78K to support booker.

TEST=build pass, check boot log with:
[booker_init] AP hash rule: 0xbe00.
BUG=b:317009620

Signed-off-by: Dehui Sun <dehui.sun@mediatek.corp-partner.google.com>
Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/mt8196/Makefile.mk

@@ -10,6 +10,7 @@ all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += timer.c timer_prepare.c
 all-y += ../common/uart.c
 
+bootblock-y += booker.c
 bootblock-y += bootblock.c
 bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += ../common/early_init.c

src/soc/mediatek/mt8196/booker.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/booker.h>
+
+#define REG_READ_ONLY_HASH_VALUE	(MCUCFG_BASE + 0x059C)
+#define REG_MCUSYS_RESERVED_REG2	(MCUCFG_BASE + 0xFFE8)
+
+#define POR_SBSX_CFG_CTL_OFFSET		(0x00450000 + 0x0A00)
+#define INSTANCE0_SBSX_POR_SBSX_CFG_CTL	(0x0A000000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE1_SBSX_POR_SBSX_CFG_CTL	(0x0A800000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE2_SBSX_POR_SBSX_CFG_CTL	(0x0B000000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE3_SBSX_POR_SBSX_CFG_CTL	(0x0B800000 + POR_SBSX_CFG_CTL_OFFSET)
+#define BIT_DISABLE_CMO_PROP		BIT(3)
+
+/*
+ * Configure booker and disable HN-D coherence request to avoid
+ * receiving NDE(Non-data Error) before MMU enabled.
+ */
+void booker_init(void)
+{
+	/* Enable CMO(cache maintenance operations) propagation */
+	clrbits64p(INSTANCE0_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE1_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE2_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE3_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	dsb();
+	isb();
+
+	/* CHI Splitter - for Q-Channel setting */
+	setbits32p(REG_MCUSYS_RESERVED_REG2, BIT(0));
+
+	printk(BIOS_DEBUG, "[%s] AP hash rule: 0x%x\n",
+	       __func__,
+	       read32p(REG_READ_ONLY_HASH_VALUE));
+}

src/soc/mediatek/mt8196/bootblock.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/booker.h>
 #include <bootblock_common.h>
 #include <soc/early_init.h>
 #include <soc/lastbus_v2.h>
@@ -9,6 +10,7 @@
 
 void bootblock_soc_init(void)
 {
+	booker_init();
 	mtk_mmu_init();
 	lastbus_init();
 	mtk_wdt_init();

src/soc/mediatek/mt8196/include/soc/booker.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8196_BOOKER_H
+#define SOC_MEDIATEK_MT8196_BOOKER_H
+
+void booker_init(void);
+
+#endif

src/soc/mediatek/mt8196/include/soc/memlayout.ld

@@ -46,7 +46,7 @@ SECTIONS
 	DRAM_INIT_CODE(0x02000000, 600K)
 	#else
 	/* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */
-	BOOTBLOCK(0x02001000, 75K)
+	BOOTBLOCK(0x02001000, 78K)
 	#endif
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
 	PRERAM_CBFS_CACHE(0x020DA000, 48K)