Because we use dummy ish in pujjoquince, so disable ish related gpio
when fw_config TABLET_MODE=TABLET_MODE_DISABLE
BUG=b:432649211
TEST=Build and boot to OS, check pujjoquince ish related gpio are closed.
Change-Id: Iab43f6d4ce3a6d31358ac0b902535ee3f5dad1e3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In 76e0f64035, it overrides
GPIO_PCH_WP in variant/gpio.h, however gpio.c includes
baseboard/gpio.h instead of variant/gpio.h. The wrong GPIO header
causes the test firmware.WriteProtectCrossystem to fail with the
wrong GPIO_PCH_WP pin number. Corrects the header file included in
gpio.c to fix the issue.
BUG=b:448313028
TEST=Pass firmware.WriteProtectCrossystem
Change-Id: I94b2384d03f8ce83f662a2b9dba4039f3d551b07
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89389
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 1e7908fa9f ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.
Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.
BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker
Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure PWR_EN and RST GPIO of fingerprint sensor.
BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.
Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Google Fatcat mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When commit 50a59d4464 ("device: Add Kconfig to prepare for reworked
verb table implementation") was created this mainboard was not in the
main branch and therefore was not accounted for. However, since it got
merged right before the commit mentioned above was merged, there was no
time to add it.
Add this Kconfig to fix the build system from failing.
Change-Id: If7382125122b4d54332f52d922d8af84ba51763c
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89368
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Seems to be the same board but with a Twin Lake processor.
VBT extracted from vendor firmware. This makes HDMI and
DisplayPort work.
Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89281
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/purism -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: I2ee7a93392a57e8194cc8116c3fc55116336234f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88686
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:
fatal1ty_z87_professional:
- 0x11020011 -> Creative CA0132[3]
It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.
The following chip names were identified using external sources:
b75m-itx:
- 0x10ec0892 -> Realtek ALC892[1][5]
b75pro3-m:
- 0x10ec0892 -> Realtek ALC892[2]
z87_extreme3:
- 0x10ec0892 -> Realtek ALC892[1][6]
z87_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][7]
z87_pro4:
- 0x10ec0892 -> Realtek ALC892[1][8]
z87e-itx:
- 0x10ec0900 -> Realtek ALC1150[4][9]
z87m_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][10]
z87m_oc_formula:
- 0x10ec0900 -> Realtek ALC1150[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asrock -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/ca0132.c:10144
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:844
[5] https://www.asrock.com/mb/Intel/B75M-ITX/index.asp
[6] https://www.asrock.com/mb/intel/Z87%20Extreme3/
[7] https://www.asrock.com/mb/intel/Z87%20Extreme4/
[8] https://www.asrock.com/mb/Intel/Z87%20Pro4/
[9] https://www.asrock.com/mb/Intel/Z87E-ITX/
[10] https://www.asrock.com/mb/Intel/Z87M%20Extreme4/index.asp
[11] https://www.asrock.com/mb/intel/z87m%20oc%20formula/
TEST= All boards passed regression test (CB:88763)
Change-Id: I60ba4e8e048dfbf8ca5969251fd448ce3644d9e0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:
macbookair4_2:
- 0x10134206 -> Cirrus Logic CS4206[1]
It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.
The Kconfigs were reverted using the following command:
find src/mainboard/apple -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] Linux kernel: sound/hda/codecs/cirrus/cs420x.c:770
TEST= All boards passed regression test (CB:88763)
Change-Id: I1fcfa0e5e1af27dc5b0dc77bf471a7636b361cbe
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/amd -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: Ie8dcff7caa24ec9f671159ea39a46989a98a6fbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88659
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:
g43t-am3:
- 0x10ec0888 -> Realtek ALC888[1]
The Kconfigs were reverted using the following command:
find src/mainboard/acer -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] coreboot board status: kernel_log.txt
TEST= All boards passed regression test (CB:88763)
Change-Id: I36cccc7033b3df523ff1c0d1891ef194090fe50e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88658
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/51nb -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: Ib77a7d097b0ae68d250ebe0cb269249a587efcb3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new Kconfig which tells the mainboard is using the "legacy" verb
table implementation. This is only needed during the transition towards
the reworked implementation, and will be removed once completed.
The Kconfigs were added manually and not with a script.
Change-Id: I3806cc8df4e244ee6542ad6796ccd9e36de557e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89174
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch enables fingerprint sensor in devicetree for ojal and updates FW config for GPIO's config according to schematics revision 0.9.
RDC kit no:840138
BUG=b:437459757
TEST=Build ojal board and check dmesg for FPS detection.
Change-Id: I44a24423f4d5b1fc85a5b3bb51f2d6646c82f9dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89324
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables ELAN touchpad in devicetree on I2C0 interface and updates FW config for GPIO's according to schematics revision 0.9.
Intel RDC kit no:840138
BUG=b:437459757
TEST=Build ojal board and test trackpad functionality
Change-Id: Idf84165877e98df31f71c8df916637a455ce84dc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch also provides valid 'io_port_mmio_base', which is the addr of
VIRT_FW_CFG device @0x1010_0000 used to convey ACPI & SMBIOS info.
TEST=build and run successfully on QEMU rvvirt machine.
Change-Id: I3cfd3020f1edacbc647188ab232c0a35dbd71f74
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This port adds support for the ASUS PRIME H610i-PLUS D4, a Mini-ITX
LGA1700 motherboard with the H610 chipset. I have been using this
port on one of these boards as my primary workstation for around
the last month, and it generally works well apart from a lack of S3
sleep. I have not yet managed to figure out the issue with that,
and have been using suspend-to-disk instead.
This board is highly similar to the H610M-K ported by Mate Kukri in
#84243, and I have included the NCT6798D fan control setup from
that patchset with minimal modification.
Working:
- Console over onboard serial port
- PS/2 keyboard
- Port 80 POST codes over ASUS debug header
- All USB ports, including USB3 working, except front USB2
- All outputs (DP, HDMI, VGA) for iGPU
- M.2 slot
- PCIe WiFi card in WiFi slot
- Onboard Ethernet
- PCIe ASPM and clock power management for all devices
- x16 PCIe slot
- All SATA ports
- Hard drive indicator LED
- All audio including front panel
- Fan control
- ME disable with HAP bit in IFD
- HSPHY-in-FMAP when ME is disabled
Untested:
- CNVi WiFi card in WiFi slot
- Front USB2 ports (did not have an adapter on hand to test)
- Status LEDs in actual error states (they do show a normal status
normally)
Not working:
- S3 sleep
Change-Id: Ib2dd2916be06dc515863df85ecb06ec043a9bc6e
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PPC64 is not functional without [OPAL] with which Linux kernel
communicates to implement important functionality like a TPM driver.
In addition to providing runtime services via OPAL Skiboot also handles
some parts of the boot process (like extracting kernel from flash) and
adjusts device tree as needed.
coreboot does not currently implement OPAL and is not likely to do it
any time soon (if ever), so must use Skiboot as a second-stage firmware
to have a fully functional PPC64 device.
mb/raptor-cs/talos-2/Kconfig is updated because Skiboot doesn't fit into
512 KiB image.
[OPAL]: https://open-power.github.io/skiboot/doc/opal-spec.html
Change-Id: I49ad6094acaccf731ab6d6b45ac103d485a3179c
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Table is from vendor.
Decrease HWEQ high pass filter from 300Hz to 125Hz.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: Id8f20af4b37cb84ec1720e7c36082c7f8cf9abb1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89284
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boardview shows the COM port header is connected to serial port A on the
super I/O chip while serial port B pins are unconnected, but it has been
coded for serial port B which cannot be correct.
Change to initialize serial port A instead.
This aligns it with other variants in the family, allowing it
to take advantage of future bootblock code unification.
Change-Id: I8c1a46bef7d9c89f423f8fea9a826b9549d783b4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable External bypass config2 for kaladin and keep FIVR settings for kelsier, and set vccin_aux_imon_iccmax to PD_TIER_VOLUME based on intel
team suggestion.
BUG=b:445829422
TEST=build and flash to DUT, check suspend_stress_test -c 1 pass
Cq-Depend:chrome-internal:8601618
Change-Id: I79e4f61c4bef9b628756a882c8d8dc0a9cb2238c
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89276
Reviewed-by: Doris <doris.hsu@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add the FW_CONFIG configuration for the Padme project of audio amp
and set up I2S for CS35L51.
BUG=b:422688421
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=Skywalker
Change-Id: I3486561dcc8695d3d3585c4844654bb7c68a2979
Signed-off-by: Youwen Huang <huangyouwen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support for MIPI panel on padme and enable TM_TL121BVMS07_00C as
the default panel. The panel uses AW37503 as the bias IC, with supply
set to ±5.9V. Add AW37503 initialization and power-on sequence are
configured according to the specification.
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
BUG=b:432353024
TEST=emerge-skywalker coreboot
Change-Id: I37a1c0352a8619ce5b10727cdeef524ccb1107ef
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89218
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the schematic diagram of lapis, refer to
the design of fatcat and modify the gpio order of mem_id.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I715634e231725bbd009b35a0c520d19a894f569c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Add HYNIX H54G46CYRBX267 as id 1, and add Samsung K3KLALA0EM-MGCU
as id 2, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
BUG=b:438785495
TEST=Use part_id_gen to generate related settings
Change-Id: I4179e31222d461b93f81c784511cc34071c10257
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This CL follow Commit 2ba74b8c18 ("mb/google/brox: Hint romstage init
about upcoming reset") CB:84937 to add PDC FW hash in variant.c to hint
romstage init about upcoming reset.
BUG=b:445606386
TEST=Build Caboc BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ie029bf7faf991f520c42ffe22e610291ba98e078
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89190
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently check_auxfw_ver_mismatch() expects the hash file to contain
only auxiliary firmware version and hence strictly checks for the size
of the auxiliary firmware version (3 bytes).
However, in some cases the hash file might contain other information
such as config_name.bin name which increases the hash file size.
Accommodate this scenario by checking the hash file size greater than
or equal to auxiliary firmware version size.
BUG=b:445606386
TEST=Build BIOS image with hash size of 3 and 11. Ensure that the
hints are provided correctly and 2 redundant resets are filtered out.
Change-Id: I287079cfc3cfbc75575ecde0603b98c57b42aa24
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The commit updates the DDR5 memory initialization parameters for the
Intel PTLRVP mainboard. Specifically, the ChannelToCkdQckMapping and
PhyClockToCkdDimm settings are overridden to ensure accurate mapping of
memory channels and PHY clocks to their respective Clock Driver and
DIMM connections.
BUG=none
TEST=Boot the PTLRVP board with DDR5 memory and verify memory
initialization.
Change-Id: I1be0a66a40e2613f10426dacd5494e345c5579db
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change allows flag to be overridden via devicetree, instead of
relying on the default value in alc711_slave. It helps fix the
missing event issue when plugging or unplugging the 3.5mm headphone
jack.
TEST=Verified build and boot with ALC721.
Headphone path switches successfully via audio jack event.
Change-Id: Ib766363fd7462bb03905fa6cba805b27d10efa04
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88867
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic diagram, lapis is designed
with five temperature detection nodes, so the initial
thermal strategy was updated.
BUG=b:438785495
TEST=emerge-fatcat coreboot
Change-Id: I908ab68766ef562ecc95085ed21658f3592937f4
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89068
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change corrects the ACPI wake event mapping for the gspi0 device,
ensuring the wake signal is routed through GPE0_DW2_19 instead of
GPE0_DW1_19. This aligns with the platform's GPIO-to-GPE mapping in
devicetree.cb
Change-Id: I2c9b0168c01c4ff8f968f0efe5bc12b650842129
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The list of changes are as follows
1. Modified USB2 port 7 from M.2 WLAN to discrete Bluetooth device.
2. Updated both Type-C ports to OC_SKIP to reflect virtual ports.
3. Adjusted Type-C port ACPI group assignments for USB3 ports.
4. Reduced display device count from 5 to 4 by removing DD04.
5. Updated comments and port usage to clarify Type-A and Type-C port
assignments.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I1e8cc92463a462c9baa78cd6d79637004340f7e2
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The FP_PRESENT probe is not required for the ISH device as they are not
in the same BDF. ISH is in the rootport 0:18:0 and gspi0 is 0:30:2.
Change-Id: I00ee0825f60719fb5a34a215780a14645def8b4c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Use fw config bit 15 to identify different ish files when enable
or disable tablet mode.
TABLET_ENABLE : pujjolo_ish.bin
TABLET_DISABLE : lite_ish.bin
BUG=b:432649211
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version
and test warmboot/coldboot/suspend pass.
Change-Id: Iffaadd5c772be6306cdcec08385de90c089f0489
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89215
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Ocelot uses the CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
because the hardware does not have DRAM ID straps, but this option was
designed for boards that would only ever have a single memory option.
In order to support multiple memory parts, we need to create a table
that maps memory part number to DRAM id so that we can select the
correct SPD for the memory, and then override the variant_memory_sku()
routine so that we can determine and return the correct DRAM id for
the memory part number specified in the CBI.
BUG=b:443646405
TEST=Change DRAM part number in CBI to "H58G66BK7BX067", reboot ocelot
and verify the AP boot logs show that the SPD index = 1.
Change-Id: I18ba6c4891c6053f40e99dcde8a06b9efc1d95f4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit updates the PCIe root port configuration for the SD card
interface in the overridetree.cb file for the Ocelot variant.
The reference is changed from `pcie_rp5` to `pcie_rp6`.
BUG=b:440042829
TEST=Boot the device with the updated firmware and verify that the
SD card is enumerated under pcie_rp6
Change-Id: I2b3c0b6e19409fef933aa7dc06f5df035f620738
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88873
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up all output GPIOs. The initial values are set consistently with
the values in kernel to avoid voltage steps in the bootup process. The
GPIOs are sorted by their EINT IDs.
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: Iacc1808108a33ca66f06ba5b3a4b082ed4e2673f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define all GPIO pins in gpio.h by their names defined in the AP pinmux
table. For example, the name of GPIO12 is "EN_PWR_FP".
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: I3936cc667d3695ff1609c3fd0fac59a204d511a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89285
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Camera sensor gets enumerated even if the hardware is not connected and
makes it available for the user, leading to a black screen when the user
tries to open the camera.
This commit changes the probing power state for the OV13B Camera Sensor
to the D0 Power State in order for the driver to validate the physical
hardware connection. This change helps prevent unnecessary enumeration
when hardware is not connected.
TEST=On a Fatcat device with an OV13B camera sensor disconnected, the OS
does not offer to use this video device.
Change-Id: Iabd8ffa6fd50367ff77325a2e1d9ae05e31eac93
Signed-off-by: Venturi Naveen <venturi.naveen@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch overrides `SkipExtGfxScan` UPD as the Fatcat device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
TEST=Able to save ~10ms+ boot time on google/fatcat.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
50b8 680462 42 76f18bda-2195-4fb6-9a940e0bacdeecab
50b9 696649 16187 76f18bda-2195-4fb6-9a940e0bacdeecab
With this patch:
`CheckOffboardPcieVga` is not getting called.
Change-Id: I198a99ac5596ff98a9cc673dbd84889d7c5386cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88888
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue with the 3.5mm headphone jack on the I2S codec AIC not detecting headphone plug/unplug events.
Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
TEST=After booting to OS, plug and unplug a headphone to the I2S codec add-in card, headphone is getting detected.
Change-Id: I263f7e9e2da0440801404dddfcf534b9ea79d470
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
