erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/skywalker: Fix incorrect GPIO_USB3_HUB_RST_L pull-down

Browse source 
commit 1e7908fa9f ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.

Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.

BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker

Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2025-10-01 02:33:19 +00:00 • committed by Yidi Lin
commit 88ad238eca
2 changed files with 2 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mainboard/google/skywalker/bootblock.c
View file

@ -8,17 +8,11 @@
#include "gpio.h"
static void usb3_hub_reset(void)
{
gpio_output(GPIO_USB3_HUB_RST_L, 1);
}
void bootblock_mainboard_init(void)
{
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS);
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
mtk_snfc_init();
usb3_hub_reset();
setup_chromeos_gpios();
gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
}

3
src/mainboard/google/skywalker/chromeos.c
View file

@ -27,7 +27,8 @@ void setup_chromeos_gpios(void)
gpio_output(GPIO_EN_SPKR, 0);
gpio_output(GPIO_RST_SPKR_L, 0);
gpio_output(GPIO_USB3_HUB_RST_L, 0);
/* Reset USB3 hub. */
gpio_output(GPIO_USB3_HUB_RST_L, 1);
gpio_output(GPIO_WWAN_RESET_L, 0);
gpio_output(GPIO_EN_PWR_FP, 0);
gpio_output(GPIO_EDP_BL_EN_1V8, 0);