erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor

Browse source 
Configure PWR_EN and RST GPIO of fingerprint sensor.

BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.

Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Hualin Wei 2025-09-23 13:49:12 +08:00 • committed by Matt DeVillier
commit b8a8800152
1 changed files with 8 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/mainboard/google/fatcat/variants/lapis/gpio.c
View file

@ -130,6 +130,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C13, NONE),
/* GPP_C14: Not used */
PAD_NC(GPP_C14, NONE),
/* GPP_C15: FP_RST_N */
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* GPP_C16: USB_C0_LSX_TX ==> TBT_LSX0_TXD */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17: USB_C0_LSX_RX ==> TBT_LSX0_RXD */
@ -232,8 +234,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE),
/* GPP_E18: TCHPAD_INT_ODL_LS ==> Not used */
PAD_NC(GPP_E18, NONE),
/* GPP_E19: Not used ==> PANEL_ID0 */
PAD_NC(GPP_E19, NONE),
/* GPP_E20: Not used ==> PANEL_ID1 */
PAD_NC(GPP_E20, NONE),
/* GPP_E21: PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */
@ -392,6 +392,12 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_C15: FP_RST_N */
PAD_CFG_GPO(GPP_C15, 0, DEEP),
/* GPP_E19: FP_PWR_EN */
PAD_CFG_GPO(GPP_E19, 1, PLTRST),
/* GPP_H08: UART0_BUF_RXD */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: UART0_BUF_TXD */