mb/google/ocelot/var/ojal: Add overridetree
BUG=b:437459757 TEST=Build ojal board Change-Id: I24086c6986bf4ba3a1ca4a208b7ce1091b392a07 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89189 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varun Upadhyay
Matt DeVillier
parent
82a9e601bd
commit
bd933b641e
4 changed files with 422 additions and 2 deletions
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@ -3,4 +3,8 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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romstage-$(CONFIG_FW_CONFIG) += fw_config.c
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ramstage-y += gpio.c
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romstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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112
src/mainboard/google/ocelot/variants/ojal/fw_config.c
Normal file
112
src/mainboard/google/ocelot/variants/ojal/fw_config.c
Normal file
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@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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#include <inttypes.h>
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/* t: base table; o: override table */
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#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
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/* t: table */
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#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
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static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
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/* GPP_H18: GEN4_SSD_PWREN */
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PAD_CFG_GPO(GPP_H18, 0, PLTRST),
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};
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static const struct pad_config gen4_ssd_pads[] = {
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/* GPP_H18: GEN4_SSD_PWREN */
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PAD_CFG_GPO(GPP_H18, 1, PLTRST),
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/* GPP_A08: M2_GEN4_SSD_RESET_N */
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PAD_CFG_GPO(GPP_A08, 1, PLTRST),
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};
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static const struct pad_config ufs_enable_pads[] = {
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/* GPP_D21: GPP_D21_UFS_REFCLK */
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PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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};
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static const struct pad_config cnvi_enable_pads[] = {
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/* GPP_B09: BT_RF_KILL_N */
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PAD_CFG_GPO(GPP_B09, 1, DEEP),
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/* GPP_C10: WIFI_RF_KILL_N */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
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/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
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/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
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/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
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/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
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/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
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/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
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/* GPP_F04: CNV_RF_RESET_R_N */
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/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
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/* GPP_F05: CRF_CLKREQ_R */
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/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
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};
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static const struct pad_config cnvi_disable_pads[] = {
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/* GPP_B09: BT_RF_KILL_N */
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PAD_NC(GPP_B09, NONE),
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/* GPP_C10: WIFI_RF_KILL_N */
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PAD_NC(GPP_C10, NONE),
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/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
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PAD_NC(GPP_F00, NONE),
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/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
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PAD_NC(GPP_F01, NONE),
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/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
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PAD_NC(GPP_F02, NONE),
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/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
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PAD_NC(GPP_F03, NONE),
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/* GPP_F04: CNV_RF_RESET_R_N */
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PAD_NC(GPP_F04, NONE),
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/* GPP_F05: CRF_CLKREQ_R */
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PAD_NC(GPP_F05, NONE),
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};
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void fw_config_configure_pre_mem_gpio(void)
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{
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if (!fw_config_is_provisioned()) {
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printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
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return;
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}
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if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
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GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
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} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
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GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
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}
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}
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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//const struct soc_intel_pantherlake_config *config = config_of_soc();
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if (!fw_config_is_provisioned()) {
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printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
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return;
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}
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if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
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} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
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} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
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GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
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}
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if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
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fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
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} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_NONE))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
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}
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}
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@ -1,5 +1,273 @@
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fw_config
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field AUDIO 0 1
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option AUDIO_NONE 0
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option AUDIO_CS42L43_SNDW 1
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option AUDIO_ALC256_HDA 2
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end
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field WIFI 2 3
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option WIFI_NONE 0
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option WIFI_CNVI_6 1
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option WIFI_CNVI_7 2
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end
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field TOUCHPAD 4 5
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option TOUCHPAD_NONE 0
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option TOUCHPAD_LPSS_I2C 1
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end
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field STORAGE 6 7
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option STORAGE_UNKNOWN 0
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option STORAGE_NVME_GEN4 1
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option STORAGE_UFS 2
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end
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field FP 8
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option FP_ABSENT 0
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option FP_PRESENT 1
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end
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field DISPLAY 9
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option DISPLAY_ABSENT 0
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option DISPLAY_PRESENT 1
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end
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field ISH 10
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option ISH_DISABLE 0
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option ISH_ENABLE 1
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end
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field KB 11
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option KB_ABSENT 0
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option KB_PRESENT 1
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end
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end
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chip soc/intel/pantherlake
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device domain 0 on
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end
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
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register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
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register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
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register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
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# Enable EDP in PortA & HDMI in Port B
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register "ddi_port_A_config" = "1"
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register "ddi_port_B_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Touchpad |
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#| I2C1 | TPM(cr50) |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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/* Render OEM footer logo 100px above from the edge */
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.logo_bottom_margin = 100,
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.early_init = 1,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref igpu on
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probe DISPLAY DISPLAY_PRESENT
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chip drivers/gfx/generic
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register "device_count" = "5"
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# DDIA for eDP
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register "device[0].name" = ""LCD0""
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register "device[0].type" = "panel"
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# DDIB for HDMI
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# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
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register "device[1].name" = ""DD01""
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# TCP0 (DP-1) for port C0
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register "device[2].name" = ""DD02""
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register "device[2].use_pld" = "true"
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register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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# TCP1 (DP-2) for port C1
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register "device[3].name" = ""DD03""
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register "device[3].use_pld" = "true"
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register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device generic 0 on end
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end
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end
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device ref iaa off end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(4, 2)"
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device ref tcss_usb3_port0 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 2)"
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device ref tcss_usb3_port1 on end
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end
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end
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end
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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use tcss_usb3_port0 as dfp[0].typec_port
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device generic 0 on end
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end
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chip drivers/intel/usb4/retimer
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register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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use tcss_usb3_port1 as dfp[1].typec_port
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device generic 0 on end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(2, 1)"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 2""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 3""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(5, 1)"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 4""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(6, 1)"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 5""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(7, 1)"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port 1""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port 2""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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device ref usb3_port2 on end
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end
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end
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end
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end
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device ref ufs on
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probe STORAGE STORAGE_UFS
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probe STORAGE STORAGE_UNKNOWN
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end
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device ref pcie_rp1 on
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probe STORAGE STORAGE_NVME_GEN4
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probe STORAGE STORAGE_UNKNOWN
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register "pcie_rp[PCIE_RP(1)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "is_storage" = "true"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end # Gen4 M.2 SSD
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device ref cnvi_wifi on
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probe WIFI WIFI_CNVI_6
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probe WIFI WIFI_CNVI_7
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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register "add_acpi_dma_property" = "true"
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register "enable_cnvi_ddr_rfim" = "true"
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use cnvi_bluetooth as bluetooth_companion
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device generic 0 on end
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end
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end # CNVi
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device ref cnvi_bluetooth on
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probe WIFI WIFI_CNVI_6
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probe WIFI WIFI_CNVI_7
|
||||
end
|
||||
|
||||
device ref i2c0 on end
|
||||
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref smbus on end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
36
src/mainboard/google/ocelot/variants/ojal/variant.c
Normal file
36
src/mainboard/google/ocelot/variants/ojal/variant.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <fsp/api.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <drivers/intel/touch/chip.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
/* CNVi */
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
|
||||
fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
|
||||
config->cnvi_wifi_core = true;
|
||||
config->cnvi_bt_core = true;
|
||||
}
|
||||
}
|
||||
|
||||
void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
|
||||
|
||||
/* HDA Audio */
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
|
||||
printk(BIOS_INFO, "Overriding HDA SDI lanes.\n");
|
||||
m_cfg->PchHdaSdiEnable[0] = true;
|
||||
m_cfg->PchHdaSdiEnable[1] = false;
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue