This commit updates the platform reporting logic to include support
for Wildcat Lake SoC.
Key changes:
- Add Wildcat Lake-specific entries for MCH, PCH, and IGD device
IDs.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ia4efb173f3ff9247d50bcfa496ed92b211729a3a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87515
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces PCI device details specific to the Wildcat
Lake to Panther Lake code with conditional compilation.
Key changes:
- Add Wildcat Lake-specific PCI device definitions and
configurations, including adjustments to device function
numbers and slot assignments.
- Remove following
- PCIe RP : 00:1c.4 to 00:1c.7
: 00:06.2 & 00:06.3
- Change following
- PCIe RP5 : 00:1c.4 to 00:06.0
- PCIe RP6 : 00:1c.5 to 00:06.1
- Following devices are not present in Wildcat Lake, but their
device definitions are retained as they do not impact
functionality.
- IPU : 00.05.0
- TBT2 : 00.07.2
- TBT3 : 00.07.3
- TCSS_XDCI : 00.0d.1
- TCSS_DMA1 : 00.0d.3
- Update Kconfig to conditionally select COMMON_BLOCK_IPU
only when SOC_INTEL_PANTHERLAKE is selected.
- Modify existing code to utilize the guards, ensuring that
Panther Lake-specific devices and configurations are only
included when appropriate.
- Add configuration options for MAX_TBT_ROOT_PORTS, MAX_ROOT_PORTS,
and MAX_PCIE_CLOCK_SRC with Wildcat Lake values.
MAX_TBT_ROOT_PORTS = 2
MAX_ROOT_PORTS = 6
MAX_PCIE_CLOCK_SRC = 6
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I89f9d9f043d3ff04c0c65dc9d92a76566e901da9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
This patch introduces a new chipset device tree file for Wildcat
Lake SoC.
Key changes:
- Copy the Panther Lake chipset.cb to chipset_wcl.cb and update
it with device information specific to the Wildcat Lake SoC.
1) Remove following devices:
- Ipu - 00:05.0
- Tbt Rp - 00:07.2 & 00:07.3
- Type-C xDCI - 00:0d.1
- Tcss Dma - 00:0d.3
- Pci Rp - 00:1c.4 to 00:1c.7
- 00:06.2 & 00:06.3
- Two TCSS USB ports
2) Remove Panther Lake Power limits config and add placeholder
for WCL config.
- Guard removed TCSS port references in the shared SoC code with
Kconfig.
- Rename Panther Lake chipset device tree to chipset_ptl.cb to
align with the new device tree naming.
- Update Kconfig to select the newly added chipset device tree
file when the Wildcat Lake SoC is in use.
References:
- Wildcat Lake Processor EDS, Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: Ieafb9856daaa48e3ecc6fc9068ae2b2d4019ff80
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87490
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If DRIVERS_WIFI_GENERIC is disabled
`wifi_generic_cnvi_ddr_rfim_enabled` can't be found by the linker.
Additionally if there is no WIFI driver the CNVi DDR RFI Mitigation is
redundant.
Add DRIVERS_WIFI_GENERIC check around `CNVi DDR RFI Mitigation`.
TEST=Boot Intel Alder Lake-P RVP with DRIVERS_WIFI_GENERIC=N and
cnvi_wifi disabled
Change-Id: I4f89ef41a730e38e08886828db0d14f1277ccaf0
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When soft-disabled, boards selecting SOC_INTEL_CSE_LITE_SKU boot up
with a working state of M3_NO_UMA vs NORMAL, so handle this condition.
Without this, when vboot is not used, the board will simply fail to
boot as vboot_recovery_mode does not exist:
[ERROR] cse_lite: CSE does not meet prerequisites
[ERROR] cse_lite: Failed to get CSE boot partition info
[DEBUG] cse: CSE status registers: HFSTS1: 0x80032044,
HFSTS2: 0x32280126 HFSTS3: 0x50
[EMERG] cse: Failed to trigger recovery mode(recovery subcode:6)
This commit addresses the first error (does not meet prerequisites),
which allows CSE sync to continue and boot the RW partition in
the soft-disabled state. It also allows the CSE to properly transition
back into the normal working state (when that option is selected via
CMOS or CFR).
TEST=build/boot google/wyvern, verify able to disable/enable the ME
properly via CFR option.
Change-Id: I46da5ac248e267acee958d66ebbd97d945e722b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87517
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When soft-disabled, boards which select SOC_INTEL_CSE_LITE_SKU boot
with their working state having a value of M3_NO_UMA (0x4), as
opposed to the "normal" value of M0_NO_UMA (0x5). Add a define for
this value (taken from older ME code in coreboot) and add a function
to check if the CSE is in that state, which will be used in a
subsequent commit.
TEST=tested with rest of patch train
Change-Id: I405987ece00b3849a9fcdf1bfc8b377fd8d010dc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87516
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit refactors the configuration options for Intel
Panther Lake SoC variants to improve clarity and maintainability.
Key changes:
- Introduce a new SOC_INTEL_PANTHERLAKE configuration option to
serve as a base selection for all Panther Lake SoC variants.
- Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to
select SOC_INTEL_PANTHERLAKE instead of
SOC_INTEL_PANTHERLAKE_BASE.
- Update existing code to utilize the new SOC_INTEL_PANTHERLAKE
guard where Panther Lake variant guards are applied.
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 12abfb43dc ("soc/intel/cnvi: Add CNVW OpRegion") added an
ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC
common northbridge.asl, but not in the ApolloLake northbridge.asl.
Add the missing GPCB function to the APL northbridge. Per Intel doc
336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.
TEST=build/boot google/ampton, verify no ACPI errors in dmesg related
to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD.
Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.
Modeled after similar patches for other SoCs.
Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some mainboards use the common DPTF ASL rather than the DPTF chip
driver, and those boards need to skip generation of the TCPU ACPI
device in order to avoid a duplicate being created and causing
issues with ACPI table parsing. Create a Kconfig that affected
boards will select to skip generating the TCPU in the SSDT.
Change-Id: Iec58d480821a273cdb4ff086f4995d21fd4bdb2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
NUM_COMx_GRP_PADS value is calculated based on COMx_GRP_PAD_END
and COMx_GRP_PAD_START values instead of using GPIO pin names.
TEST=Compiled and Verified on Wildcat Lake Simulation Platform.
Change-Id: I0c5b2ebc00f328bd4b9df4653d5339781e38fcba
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Key changes:
- Relocate the package corresponding to CPUJTAG group from GPI3
device to the GPI4 device in the ACPI table, utilizing a Kconfig
guard for conditional compilation.
- Add ACPI IDs specific to Wildcat Lake GPIO communities.
- Select SOC_INTEL_PANTHERLAKE_BASE for SOC_INTEL_WILDCATLAKE to
clearly differentiate between Panther Lake and Wildcat Lake
changes.
References:
- Wildcat Lake EDS Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: I934c193c75e459c72cc8b01a575cc0bbd65dc273
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces GPIO changes for the Wildcat Lake SoC.
These changes coexist with the Panther Lake SoC GPIO files.
Key Changes:
- The CPUJTAG group is moved from community 3 to community 4.
- A new pin is added to Group H.
- Wildcat Lake-specific register definitions are included.
- Kconfig is utilized to segregate Wildcat Lake GPIO changes.
References:
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: Ib364d41097c53cd085c6cf89b0461ce38117b21e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Sending the disable and EOP commands will not work if flash descriptor
override is set on Meteor Lake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <Jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This commit updates the pre-allocated IGD stolen memory size for Intel
Panther Lake SoCs from 128MB to 64MB within the FSP-M configuration
parameters.
Reducing the IGD stolen memory allocation from 128MB to 64MB
significantly optimizes system memory resource utilization (by 64MB).
Furthermore, this reduction frees one MTRR. Previously, the 128MB IGD
allocation consumed all 10 available BIOS MTRRs; the new 64MB allocation
now leaves MTRR index 9 available.
BUG=b:413638298
TEST=Able to boot google/fatcat to OS w/ internal and/or external
display attached.
Change-Id: Ifd60973bc5d37cbbc4ea6c8eaf5d851069d53083
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87460
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit refactors the HDA initialization within the common Intel
SoC block to provide mainboard-level customization.
A new weak function, mainboard_is_hda_codec_enabled(), is
introduced. The `hda_init()` function invokes `azalia_audio_init()` when
`CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)` is enabled and
`mainboard_is_hda_codec_enabled()` is also true.
The default (weak) implementation of `mainboard_is_hda_codec_enabled()`
simply returns `true`, ensuring that the original behavior is maintained
for mainboards that do not provide an override.
This change allows specific mainboards to implement their own
`mainboard_is_hda_codec_enabled()` to specify if hardware design has
support for HDA codec depending upon the firmware config (FW_CONFIG) for
the audio subsystem.
BUG=b:413638298
TEST=Able to build and boot google/fatcat.
Change-Id: Ided1413e828f6bc3421e538a969c38e15b5f3116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot google/guado with CFR options enabled.
Change-Id: Iaf9950a3b446b1b55d836e54e8b231d047571768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87387
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I925002958b5de93e833f06fddf772e5334a7bdb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Iaddaf56563bd5916bc27d99171af48bf46127052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87399
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because CNVi takes around 300ms to initialize after the GPIO is
enabled.
Change-Id: I53986aa11714666c12056460aa47396266a00a1c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.
These values can be seen in SlimBootloader, and most UEFI firmwares.
Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch overrides the FSP-M UART MMIO base address to ensure the FSP
GFX PEIM can output debug console messages when required.
Currently, the default UART MMIO base used by FSP-M/S might not be the
intended console UART for debug output in boot stages, particularly for
the GFX PEIM. By overriding it with the value derived from
`CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or
`SerialDebugMrcLevel` is non-zero, we ensure that debug logs are
directed to the configured console.
This change is crucial for debugging issues within the GFX PEIM
initialization process.
BUG=b:380375181
TEST=Verified that enabling FSP debug tokens after this change allows
viewing debug output from the GFX PEIM during display initialization.
Steps to reproduce:
1. Flash an AP FW image (`image.fatcat.serial.bin`).
2. Observe the absence of debug output from the GFX PEIM during display
initialization.
3. Dynamically enable the FSP debug token using
```
sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level
```
4. Flash the modified AP FW image.
5. Observe debug output from the GFX PEIM during display initialization
```
[INFO]:[IsGraphicsDeviceSupported()]...
[INFO]:[GetVbtStartAddress()]
```
Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.
Based on Intel docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Based on the description of PMC GPIO_CONF register from
EHL EDS Vol 2 Book 2 rev 2.3 #614109.
Some of the groups had incorrect values or even defined
non-existent GPIO groups.
TEST=Boot Protectli VP2420 to Ubuntu 24.04.
Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87050
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.
BUG=NA
TEST=Customer platform with Raptorlake-P
Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Intel processor number X7433RE.
Based on docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for
Panther Lake SoC has been removed.
Panther Lake platforms inherently enable display across all boot
modes (normal, developer, recovery) when vboot is active.
Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY`
becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY`
is enabled due to the selection of `BMP_LOGO` for ChromeOS
devices.
TEST=Able to perform ec sync without any additional reboots.
Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a conditional bypass for ME state setting,
potentially reducing CBFS traversal time when searching for the
`option/me_state` file.
TEST=Able to build and boot google/fatcat.
Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the default heap size from 1MB to 2MB (0x200000) to
accommodate rendering high-quality firmware splash BMP logos.
The previous 1MB heap size might be insufficient for larger, more
detailed OEM logos, potentially leading to memory exhaustion during the
splash screen display.
TEST=Able to render an OEM logo size ~512KB w/o any corruption.
Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87265
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported.
The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards.
This option was previously enabled at the SoC level for Pantherlake,
but is now being enabled specifically for these mainboards.
BUG=b:400550435
TEST=Build the Fatcat and Felino targets. Verify that the eSOL works
fine.
Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87236
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The Kconfig options `USE_INTEL_FSP_MP_INIT` and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually
exclusive ways for the FSP to handle MP initialization.
This commit updates the `default` condition for
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if
!USE_INTEL_FSP_MP_INIT`. This ensures that if
`USE_INTEL_FSP_MP_INIT` is enabled,
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default
to disabled, preventing potential conflicts in MP initialization.
The explicit `depends on
!USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI`
on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to
this change in the default value, but it is kept for clarity and
to explicitly state the mutual exclusivity.
TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for
google/fatcat.
Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
