soc/intel/apollolake/acpi: Add function to get PCIe BAR

Commit 12abfb43dc ("soc/intel/cnvi: Add CNVW OpRegion") added an
ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC
common northbridge.asl, but not in the ApolloLake northbridge.asl.

Add the missing GPCB function to the APL northbridge. Per Intel doc
336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.

TEST=build/boot google/ampton, verify no ACPI errors in dmesg related
to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD.

Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/acpi/northbridge.asl

@@ -124,5 +124,12 @@ Device (PDRC)	/* PCI Device Resource Consumption */
 	}
 }
 
+/* Get PCIe BAR */
+Method (GPCB, 0, Serialized)
+{
+	Local0 = \_SB.PCI0.MCHC.PXBR << 28
+	Return (Local0)
+}
+
 /* GFX 00:02.0 */
 #include <drivers/intel/gma/acpi/gfx.asl>