soc/intel/cannonlake: Hook up DPTF device to devicetree

Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.

Modeled after similar patches for other SoCs.

Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -68,9 +68,7 @@ chip soc/intel/cannonlake
 				.backlight_off_delay_ms	=    1,
 			}"
 		end
-		device ref dptf on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf on	end
 		device ref thermal on	end
 		device ref xhci on
 			# USB2

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -46,7 +46,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 140,
 	}"
-	register "Device4Enable" = "1"
 	register "AcousticNoiseMitigation" = "1"
 	register "SlowSlewRateForIa" = "2"
 	register "SlowSlewRateForGt" = "2"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -195,6 +194,7 @@ chip soc/intel/cannonlake
 
 	device domain 0 on
 		device ref igpu		on end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on
 			chip drivers/usb/acpi

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -195,6 +194,7 @@ chip soc/intel/cannonlake
 
 	device domain 0 on
 		device ref igpu		on end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on
 			chip drivers/usb/acpi

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -35,7 +35,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 140,
 	}"
-	register "Device4Enable" = "1"
 	register "AcousticNoiseMitigation" = "1"
 	register "SlowSlewRateForIa" = "2"
 	register "SlowSlewRateForGt" = "2"

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -43,7 +43,6 @@ chip soc/intel/cannonlake
 		.tdp_pl2_override = 51,
 		.psys_pmax = 136,
 	}"
-	register "Device4Enable" = "1"
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C

src/mainboard/purism/librem_cnl/devicetree.cb

@@ -43,9 +43,7 @@ chip soc/intel/cannonlake
 # Actual device tree
 	device domain 0 on
 		device ref igpu		on end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on end
 		device ref thermal	on end
 		device ref xhci		on end
 		device ref sata		on end

src/mainboard/system76/addw1/devicetree.cb

@@ -57,9 +57,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
 		device ref igpu		on	end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{

src/mainboard/system76/cml-u/devicetree.cb

@@ -60,9 +60,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref cnvi_wifi	on
 			chip drivers/wifi/generic

src/mainboard/system76/gaze15/devicetree.cb

@@ -58,9 +58,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{

src/mainboard/system76/oryp5/devicetree.cb

@@ -66,9 +66,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{

src/mainboard/system76/oryp6/devicetree.cb

@@ -63,9 +63,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on
 			register "usb2_ports" = "{

src/mainboard/system76/whl-u/devicetree.cb

@@ -60,9 +60,7 @@ chip soc/intel/cannonlake
 		device ref igpu		on
 			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 		end
-		device ref dptf		on
-			register "Device4Enable" = "1"
-		end
+		device ref dptf		on  end
 		device ref thermal	on  end
 		device ref xhci		on
 			register "usb2_ports" = "{

src/soc/intel/cannonlake/chip.h

@@ -220,8 +220,6 @@ struct soc_intel_cannonlake_config {
 	/* Gfx related */
 	bool SkipExtGfxScan;
 
-	bool Device4Enable;
-
 	/* CPU PL2/4 Config
 	 * Performance: Maximum PLs for maximum performance.
 	 * Baseline: Baseline PLs for balanced performance at lower power.

src/soc/intel/cannonlake/fsp_params.c

@@ -631,7 +631,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * the `Heci1Disabled` UPD to `0`.
 	 */
 	s_cfg->Heci1Disabled = 0;
-	s_cfg->Device4Enable = config->Device4Enable;
+	s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_TS);
 
 	/* Teton Glacier hybrid storage support */
 	s_cfg->TetonGlacierMode = config->TetonGlacierMode;