device/pci_ids: Add Amston Lake CPU IDs

Intel processor number X7433RE.
Based on docs 721616 rev 2.3.

BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor

Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>

src/include/device/pci_ids.h

@@ -4427,6 +4427,9 @@
 #define PCI_DID_INTEL_ADL_N_ID_7		0x4679
 #define PCI_DID_INTEL_ADL_N_ID_8		0x467C
 #define PCI_DID_INTEL_ADL_N_ID_9		0x4677
+#define PCI_DID_INTEL_ASL_ID_1			0x4632
+#define PCI_DID_INTEL_ASL_ID_2			0x4674
+#define PCI_DID_INTEL_ASL_ID_3			0x4675
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02

src/soc/intel/alderlake/bootblock/report_platform.c

@@ -81,6 +81,9 @@ static struct {
 	{ PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" },
 	{ PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" },
 	{ PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" },
+	{ PCI_DID_INTEL_ASL_ID_1, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_2, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_3, "Amstonlake" },
 	{ PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" },
 	{ PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" },
 	{ PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" },
@@ -110,6 +113,7 @@ static struct {
 } pch_table[] = {
 	{ PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
 	{ PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_ADP_M_N_ESPI_10, "Amstonlake SKU" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_H610E, "AlderLake-S H610E" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_Q670E, "AlderLake-S Q670E" },
 	{ PCI_DID_INTEL_ADP_S_ESPI_R680E, "AlderLake-S R680E" },

src/soc/intel/alderlake/cpu.c

@@ -249,6 +249,12 @@ enum adl_cpu_type get_adl_cpu_type(void)
 		PCI_DID_INTEL_ADL_N_ID_9,
 	};
 
+	const uint16_t asl_mch_ids[] = {
+		PCI_DID_INTEL_ASL_ID_1,
+		PCI_DID_INTEL_ASL_ID_2,
+		PCI_DID_INTEL_ASL_ID_3,
+	};
+
 	const uint16_t rpl_hx_mch_ids[] = {
 		PCI_DID_INTEL_RPL_HX_ID_1,
 		PCI_DID_INTEL_RPL_HX_ID_2,
@@ -298,6 +304,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
 			return ADL_S;
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(asl_mch_ids); i++) {
+		if (asl_mch_ids[i] == mchid)
+			return ASL;
+	}
+
 	for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) {
 		if (rpl_s_mch_ids[i] == mchid)
 			return RPL_S;
@@ -332,6 +343,7 @@ uint8_t get_supported_lpm_mask(void)
 	case ADL_M: /* fallthrough */
 	case ADL_N:
 	case ADL_P:
+	case ASL:
 	case RPL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:

src/soc/intel/alderlake/fsp_params.c

@@ -518,6 +518,9 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi
 	case PCI_DID_INTEL_ADL_S_ID_10:
 	case PCI_DID_INTEL_ADL_S_ID_11:
 	case PCI_DID_INTEL_ADL_S_ID_12:
+	case PCI_DID_INTEL_ASL_ID_1:
+	case PCI_DID_INTEL_ASL_ID_2:
+	case PCI_DID_INTEL_ASL_ID_3:
 	case PCI_DID_INTEL_RPL_HX_ID_1:
 	case PCI_DID_INTEL_RPL_HX_ID_2:
 	case PCI_DID_INTEL_RPL_HX_ID_3:

src/soc/intel/alderlake/include/soc/cpu.h

@@ -25,6 +25,7 @@ enum adl_cpu_type {
 	ADL_N,
 	ADL_P,
 	ADL_S,
+	ASL,
 	RPL_HX,
 	RPL_P,
 	RPL_S,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -538,6 +538,9 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_ADL_N_ID_7,
 	PCI_DID_INTEL_ADL_N_ID_8,
 	PCI_DID_INTEL_ADL_N_ID_9,
+	PCI_DID_INTEL_ASL_ID_1,
+	PCI_DID_INTEL_ASL_ID_2,
+	PCI_DID_INTEL_ASL_ID_3,
 	PCI_DID_INTEL_RPL_HX_ID_1,
 	PCI_DID_INTEL_RPL_HX_ID_2,
 	PCI_DID_INTEL_RPL_HX_ID_3,