soc/intel: Add Wildcat Lake CPU and PCIe device IDs

This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.

Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)

BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform

Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/ish/ish.c

@@ -85,6 +85,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_ISHB,
 	PCI_DID_INTEL_PTL_H_ISHB,
 	PCI_DID_INTEL_PTL_U_H_ISHB,
 	PCI_DID_INTEL_LNL_ISHB,

src/drivers/intel/touch/touch.c

@@ -581,6 +581,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_THC0_SPI,
 	PCI_DID_INTEL_PTL_H_THC1_I2C,
 	PCI_DID_INTEL_PTL_H_THC1_SPI,
+	PCI_DID_INTEL_WCL_THC0_I2C,
+	PCI_DID_INTEL_WCL_THC0_SPI,
+	PCI_DID_INTEL_WCL_THC1_I2C,
+	PCI_DID_INTEL_WCL_THC1_SPI,
 	0
 };
 

src/include/cpu/intel/cpu_ids.h

@@ -92,5 +92,6 @@
 #define CPUID_SNOWRIDGE_B0		0x80664
 #define CPUID_SNOWRIDGE_B1		0x80665
 #define CPUID_SNOWRIDGE_C0		0x80667
+#define CPUID_WILDCATLAKE_A0		0xd0650
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -2187,6 +2187,7 @@
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
 #define PCI_DID_INTEL_PTL_H_ISHB	0xe445
 #define PCI_DID_INTEL_PTL_U_H_ISHB	0xe345
+#define PCI_DID_INTEL_WCL_ISHB		0x4d45
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3246,6 +3247,38 @@
 #define PCI_DID_INTEL_PTL_U_H_ESPI_30			0xe31e
 #define PCI_DID_INTEL_PTL_U_H_ESPI_31			0xe31f
 #define PCI_DID_INTEL_SNR_LPC					0x18dc
+#define PCI_DID_INTEL_WCL_ESPI_0			0x4d00
+#define PCI_DID_INTEL_WCL_ESPI_1			0x4d01
+#define PCI_DID_INTEL_WCL_ESPI_2			0x4d02
+#define PCI_DID_INTEL_WCL_ESPI_3			0x4d03
+#define PCI_DID_INTEL_WCL_ESPI_4			0x4d04
+#define PCI_DID_INTEL_WCL_ESPI_5			0x4d05
+#define PCI_DID_INTEL_WCL_ESPI_6			0x4d06
+#define PCI_DID_INTEL_WCL_ESPI_7			0x4d07
+#define PCI_DID_INTEL_WCL_ESPI_8			0x4d08
+#define PCI_DID_INTEL_WCL_ESPI_9			0x4d09
+#define PCI_DID_INTEL_WCL_ESPI_10			0x4d0a
+#define PCI_DID_INTEL_WCL_ESPI_11			0x4d0b
+#define PCI_DID_INTEL_WCL_ESPI_12			0x4d0c
+#define PCI_DID_INTEL_WCL_ESPI_13			0x4d0d
+#define PCI_DID_INTEL_WCL_ESPI_14			0x4d0e
+#define PCI_DID_INTEL_WCL_ESPI_15			0x4d0f
+#define PCI_DID_INTEL_WCL_ESPI_16			0x4d10
+#define PCI_DID_INTEL_WCL_ESPI_17			0x4d11
+#define PCI_DID_INTEL_WCL_ESPI_18			0x4d12
+#define PCI_DID_INTEL_WCL_ESPI_19			0x4d13
+#define PCI_DID_INTEL_WCL_ESPI_20			0x4d14
+#define PCI_DID_INTEL_WCL_ESPI_21			0x4d15
+#define PCI_DID_INTEL_WCL_ESPI_22			0x4d16
+#define PCI_DID_INTEL_WCL_ESPI_23			0x4d17
+#define PCI_DID_INTEL_WCL_ESPI_24			0x4d18
+#define PCI_DID_INTEL_WCL_ESPI_25			0x4d19
+#define PCI_DID_INTEL_WCL_ESPI_26			0x4d1a
+#define PCI_DID_INTEL_WCL_ESPI_27			0x4d1b
+#define PCI_DID_INTEL_WCL_ESPI_28			0x4d1c
+#define PCI_DID_INTEL_WCL_ESPI_29			0x4d1d
+#define PCI_DID_INTEL_WCL_ESPI_30			0x4d1e
+#define PCI_DID_INTEL_WCL_ESPI_31			0x4d1f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3681,6 +3714,13 @@
 #define PCI_DID_INTEL_SNR_PCH_PCIE_RP10			0x18af
 #define PCI_DID_INTEL_SNR_PCH_PCIE_RP11			0x18a2
 
+#define PCI_DID_INTEL_WCL_PCIE_RP1                      0x4d3c
+#define PCI_DID_INTEL_WCL_PCIE_RP2                      0x4d3d
+#define PCI_DID_INTEL_WCL_PCIE_RP3                      0x4d3e
+#define PCI_DID_INTEL_WCL_PCIE_RP4                      0x4d3f
+#define PCI_DID_INTEL_WCL_PCIE_RP5                      0x4d61
+#define PCI_DID_INTEL_WCL_PCIE_RP6                      0x4d5c
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3799,6 +3839,7 @@
 #define PCI_DID_INTEL_LNL_PMC			0xa821
 #define PCI_DID_INTEL_PTL_H_PMC			0xe421
 #define PCI_DID_INTEL_PTL_U_H_PMC		0xe321
+#define PCI_DID_INTEL_WCL_PMC			0x4d21
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -3943,6 +3984,13 @@
 #define PCI_DID_INTEL_PTL_U_H_I2C4		0xe350
 #define PCI_DID_INTEL_PTL_U_H_I2C5		0xe351
 
+#define PCI_DID_INTEL_WCL_I2C0			0x4d78
+#define PCI_DID_INTEL_WCL_I2C1			0x4d79
+#define PCI_DID_INTEL_WCL_I2C2			0x4d7a
+#define PCI_DID_INTEL_WCL_I2C3			0x4d7b
+#define PCI_DID_INTEL_WCL_I2C4			0x4d50
+#define PCI_DID_INTEL_WCL_I2C5			0x4d51
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -4033,6 +4081,10 @@
 #define PCI_DID_INTEL_PTL_U_H_UART1		0xe326
 #define PCI_DID_INTEL_PTL_U_H_UART2		0xe352
 
+#define PCI_DID_INTEL_WCL_UART0			0x4d25
+#define PCI_DID_INTEL_WCL_UART1			0x4d26
+#define PCI_DID_INTEL_WCL_UART2			0x4d52
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -4143,6 +4195,11 @@
 
 #define PCI_DID_INTEL_SNR_SPI			0x18e0
 
+#define PCI_DID_INTEL_WCL_HWSEQ_SPI		0x4d23
+#define PCI_DID_INTEL_WCL_SPI0			0x4d27
+#define PCI_DID_INTEL_WCL_SPI1			0x4d30
+#define PCI_DID_INTEL_WCL_SPI2			0x4d46
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -4310,6 +4367,8 @@
 #define PCI_DID_INTEL_PTL_H_GT2_1			0xb080
 #define PCI_DID_INTEL_PTL_H_GT2_2			0xb0a0
 #define PCI_DID_INTEL_PTL_H_GT2_3			0xb0b0
+#define PCI_DID_INTEL_WCL_GT2_1				0xfd80
+#define PCI_DID_INTEL_WCL_GT2_2				0xfd81
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4466,6 +4525,8 @@
 #define PCI_DID_INTEL_PTL_H_ID_3		0xb004
 #define PCI_DID_INTEL_PTL_H_ID_4		0xb00a
 #define PCI_DID_INTEL_SNR_ID			0x09a2
+#define PCI_DID_INTEL_WCL_ID_1			0xfd00
+#define PCI_DID_INTEL_WCL_ID_2			0xfd01
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4497,6 +4558,7 @@
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
 #define PCI_DID_INTEL_PTL_H_SMBUS			0xe422
 #define PCI_DID_INTEL_PTL_U_H_SMBUS			0xe322
+#define PCI_DID_INTEL_WCL_SMBUS				0x4d22
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4544,6 +4606,8 @@
 #define PCI_DID_INTEL_PTL_U_H_XHCI		0xe37d
 #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI		0xe331
 #define PCI_DID_INTEL_SNR_XHCI			0x18d0
+#define PCI_DID_INTEL_WCL_XHCI			0x4d7d
+#define PCI_DID_INTEL_WCL_TCSS_XHCI		0x4d31
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4577,6 +4641,8 @@
 #define PCI_DID_INTEL_PTL_U_H_P2SB		0xe320
 #define PCI_DID_INTEL_PTL_U_H_P2SB2		0xe34c
 #define PCI_DID_INTEL_SNR_P2SB			0x18dd
+#define PCI_DID_INTEL_WCL_P2SB			0x4d20
+#define PCI_DID_INTEL_WCL_P2SB2			0x4d4c
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4594,6 +4660,7 @@
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
+#define PCI_DID_INTEL_WCL_SRAM			0x4d7f
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4677,6 +4744,15 @@
 #define PCI_DID_INTEL_PTL_U_H_AUDIO_7		0xe32e
 #define PCI_DID_INTEL_PTL_U_H_AUDIO_8		0xe32f
 
+#define PCI_DID_INTEL_WCL_AUDIO_1		0x4d28
+#define PCI_DID_INTEL_WCL_AUDIO_2		0x4d29
+#define PCI_DID_INTEL_WCL_AUDIO_3		0x4d2a
+#define PCI_DID_INTEL_WCL_AUDIO_4		0x4d2b
+#define PCI_DID_INTEL_WCL_AUDIO_5		0x4d2c
+#define PCI_DID_INTEL_WCL_AUDIO_6		0x4d2d
+#define PCI_DID_INTEL_WCL_AUDIO_7		0x4d2e
+#define PCI_DID_INTEL_WCL_AUDIO_8		0x4d2f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_H_MEI_9		0x8cba
@@ -4725,6 +4801,7 @@
 #define PCI_DID_INTEL_PTL_H_CSE0		0xe470
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
 #define PCI_DID_INTEL_SNR_HECI1			0x18d3
+#define PCI_DID_INTEL_WCL_CSE0			0x4d70
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -4750,6 +4827,7 @@
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
+#define PCI_DID_INTEL_WCL_XDCI		0x4d7e
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4810,6 +4888,7 @@
 #define PCI_DID_INTEL_LNL_TBT_DMA1		0xa834
 #define PCI_DID_INTEL_PTL_TBT_DMA0		0xe433
 #define PCI_DID_INTEL_PTL_TBT_DMA1		0xe434
+#define PCI_DID_INTEL_WCL_TBT_DMA0		0x4d33
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4861,6 +4940,7 @@
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
 #define PCI_DID_INTEL_RPL_DTT			0xa71d
 #define PCI_DID_INTEL_PTL_DTT			0xb01d
+#define PCI_DID_INTEL_WCL_DTT			0xfd1d
 
 /* Intel CNVi WiFi/BT device IDs */
 #define PCI_DID_INTEL_CML_LP_CNVI_WIFI		0x02f0
@@ -4922,11 +5002,19 @@
 #define PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_2	0xe342
 #define PCI_DID_INTEL_PTL_U_H_CNVI_WIFI_3	0xe343
 #define PCI_DID_INTEL_PTL_U_H_CNVI_BT		0xe376
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_0		0x4d40
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_1		0x4d41
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_2		0x4d42
+#define PCI_DID_INTEL_WCL_CNVI_WIFI_3		0x4d43
+#define PCI_DID_INTEL_WCL_CNVI_BT		0x4d76
 
 /* Platform Security Engine */
 #define PCI_DID_INTEL_LNL_PSE0			0xa862
 #define PCI_DID_INTEL_LNL_PSE1			0xa863
 #define PCI_DID_INTEL_LNL_PSE2			0xa864
+#define PCI_DID_INTEL_WCL_PSE0			0x4d62
+#define PCI_DID_INTEL_WCL_PSE1			0x4d63
+#define PCI_DID_INTEL_WCL_PSE2			0x4d64
 
 /* In-memory Analytics Accelerator device IDs */
 #define PCI_DID_INTEL_LNL_IAA			0x642d
@@ -4942,12 +5030,14 @@
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
+#define PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM		0xfd7d
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
 #define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
+#define PCI_DID_INTEL_WCL_TRACEHUB			0x4d24
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32
@@ -4967,6 +5057,10 @@
 #define PCI_DID_INTEL_PTL_H_THC0_SPI	0xe449
 #define PCI_DID_INTEL_PTL_H_THC1_I2C	0xe44a
 #define PCI_DID_INTEL_PTL_H_THC1_SPI	0xe44b
+#define PCI_DID_INTEL_WCL_THC0_I2C	0x4d48
+#define PCI_DID_INTEL_WCL_THC0_SPI	0x4d49
+#define PCI_DID_INTEL_WCL_THC1_I2C	0x4d4a
+#define PCI_DID_INTEL_WCL_THC1_SPI	0x4d4b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291

src/soc/intel/common/block/cnvi/cnvi.c

@@ -422,6 +422,10 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CNVI_WIFI_0,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_1,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_2,
+	PCI_DID_INTEL_WCL_CNVI_WIFI_3,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_0,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_1,
 	PCI_DID_INTEL_PTL_H_CNVI_WIFI_2,
@@ -496,6 +500,7 @@ static struct device_operations cnvi_bt_ops = {
 };
 
 static const unsigned short bt_pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CNVI_BT,
 	PCI_DID_INTEL_PTL_H_CNVI_BT,
 	PCI_DID_INTEL_PTL_U_H_CNVI_BT,
 	PCI_DID_INTEL_TGL_CNVI_BT_0,

src/soc/intel/common/block/cpu/mp_init.c

@@ -32,6 +32,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, CPUID_WILDCATLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },

src/soc/intel/common/block/cse/cse.c

@@ -1512,6 +1512,7 @@ struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_CSE0,
 	PCI_DID_INTEL_PTL_H_CSE0,
 	PCI_DID_INTEL_PTL_U_H_CSE0,
 	PCI_DID_INTEL_LNL_CSE0,

src/soc/intel/common/block/dsp/dsp.c

@@ -13,6 +13,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_AUDIO_1,
+	PCI_DID_INTEL_WCL_AUDIO_2,
+	PCI_DID_INTEL_WCL_AUDIO_3,
+	PCI_DID_INTEL_WCL_AUDIO_4,
+	PCI_DID_INTEL_WCL_AUDIO_5,
+	PCI_DID_INTEL_WCL_AUDIO_6,
+	PCI_DID_INTEL_WCL_AUDIO_7,
+	PCI_DID_INTEL_WCL_AUDIO_8,
 	PCI_DID_INTEL_PTL_H_AUDIO_1,
 	PCI_DID_INTEL_PTL_H_AUDIO_2,
 	PCI_DID_INTEL_PTL_H_AUDIO_3,

src/soc/intel/common/block/dtt/dtt.c

@@ -8,6 +8,7 @@
 #include <intelblocks/acpi.h>
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_DTT,
 	PCI_DID_INTEL_PTL_DTT,
 	PCI_DID_INTEL_RPL_DTT,
 	PCI_DID_INTEL_MTL_DTT,

src/soc/intel/common/block/graphics/graphics.c

@@ -342,6 +342,8 @@ const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_GT2_1,
+	PCI_DID_INTEL_WCL_GT2_2,
 	PCI_DID_INTEL_PTL_U_GT2_1,
 	PCI_DID_INTEL_PTL_H_GT2_1,
 	PCI_DID_INTEL_PTL_H_GT2_2,

src/soc/intel/common/block/hda/hda.c

@@ -21,6 +21,14 @@ struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_AUDIO_1,
+	PCI_DID_INTEL_WCL_AUDIO_2,
+	PCI_DID_INTEL_WCL_AUDIO_3,
+	PCI_DID_INTEL_WCL_AUDIO_4,
+	PCI_DID_INTEL_WCL_AUDIO_5,
+	PCI_DID_INTEL_WCL_AUDIO_6,
+	PCI_DID_INTEL_WCL_AUDIO_7,
+	PCI_DID_INTEL_WCL_AUDIO_8,
 	PCI_DID_INTEL_PTL_H_AUDIO_1,
 	PCI_DID_INTEL_PTL_H_AUDIO_2,
 	PCI_DID_INTEL_PTL_H_AUDIO_3,

src/soc/intel/common/block/i2c/i2c.c

@@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_I2C0,
+	PCI_DID_INTEL_WCL_I2C1,
+	PCI_DID_INTEL_WCL_I2C2,
+	PCI_DID_INTEL_WCL_I2C3,
+	PCI_DID_INTEL_WCL_I2C4,
+	PCI_DID_INTEL_WCL_I2C5,
 	PCI_DID_INTEL_PTL_H_I2C0,
 	PCI_DID_INTEL_PTL_H_I2C1,
 	PCI_DID_INTEL_PTL_H_I2C2,

src/soc/intel/common/block/lpc/lpc.c

@@ -151,6 +151,38 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_ESPI_0,
+	PCI_DID_INTEL_WCL_ESPI_1,
+	PCI_DID_INTEL_WCL_ESPI_2,
+	PCI_DID_INTEL_WCL_ESPI_3,
+	PCI_DID_INTEL_WCL_ESPI_4,
+	PCI_DID_INTEL_WCL_ESPI_5,
+	PCI_DID_INTEL_WCL_ESPI_6,
+	PCI_DID_INTEL_WCL_ESPI_7,
+	PCI_DID_INTEL_WCL_ESPI_8,
+	PCI_DID_INTEL_WCL_ESPI_9,
+	PCI_DID_INTEL_WCL_ESPI_10,
+	PCI_DID_INTEL_WCL_ESPI_11,
+	PCI_DID_INTEL_WCL_ESPI_12,
+	PCI_DID_INTEL_WCL_ESPI_13,
+	PCI_DID_INTEL_WCL_ESPI_14,
+	PCI_DID_INTEL_WCL_ESPI_15,
+	PCI_DID_INTEL_WCL_ESPI_16,
+	PCI_DID_INTEL_WCL_ESPI_17,
+	PCI_DID_INTEL_WCL_ESPI_18,
+	PCI_DID_INTEL_WCL_ESPI_19,
+	PCI_DID_INTEL_WCL_ESPI_20,
+	PCI_DID_INTEL_WCL_ESPI_21,
+	PCI_DID_INTEL_WCL_ESPI_22,
+	PCI_DID_INTEL_WCL_ESPI_23,
+	PCI_DID_INTEL_WCL_ESPI_24,
+	PCI_DID_INTEL_WCL_ESPI_25,
+	PCI_DID_INTEL_WCL_ESPI_26,
+	PCI_DID_INTEL_WCL_ESPI_27,
+	PCI_DID_INTEL_WCL_ESPI_28,
+	PCI_DID_INTEL_WCL_ESPI_29,
+	PCI_DID_INTEL_WCL_ESPI_30,
+	PCI_DID_INTEL_WCL_ESPI_31,
 	PCI_DID_INTEL_PTL_U_H_ESPI_0,
 	PCI_DID_INTEL_PTL_U_H_ESPI_1,
 	PCI_DID_INTEL_PTL_U_H_ESPI_2,

src/soc/intel/common/block/p2sb/ioe_p2sb.c

@@ -37,6 +37,7 @@ struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB2,
 	PCI_DID_INTEL_PTL_H_P2SB2,
 	PCI_DID_INTEL_PTL_U_H_P2SB2,
 	PCI_DID_INTEL_MTL_IOE_M_P2SB,

src/soc/intel/common/block/p2sb/p2sb.c

@@ -137,6 +137,7 @@ const struct device_operations p2sb_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB,
 	PCI_DID_INTEL_PTL_H_P2SB,
 	PCI_DID_INTEL_PTL_U_H_P2SB,
 	PCI_DID_INTEL_LNL_P2SB,

src/soc/intel/common/block/pcie/pcie.c

@@ -67,6 +67,12 @@ struct device_operations pcie_rp_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_WCL_PCIE_RP1,
+	PCI_DID_INTEL_WCL_PCIE_RP2,
+	PCI_DID_INTEL_WCL_PCIE_RP3,
+	PCI_DID_INTEL_WCL_PCIE_RP4,
+	PCI_DID_INTEL_WCL_PCIE_RP5,
+	PCI_DID_INTEL_WCL_PCIE_RP6,
 	PCI_DID_INTEL_PTL_H_PCIE_RP1,
 	PCI_DID_INTEL_PTL_H_PCIE_RP2,
 	PCI_DID_INTEL_PTL_H_PCIE_RP3,

src/soc/intel/common/block/pmc/pmc.c

@@ -111,6 +111,7 @@ struct device_operations pmc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_PMC,
 	PCI_DID_INTEL_PTL_H_PMC,
 	PCI_DID_INTEL_PTL_U_H_PMC,
 	PCI_DID_INTEL_LNL_PMC,

src/soc/intel/common/block/smbus/smbus.c

@@ -49,6 +49,7 @@ struct device_operations smbus_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_SMBUS,
 	PCI_DID_INTEL_PTL_H_SMBUS,
 	PCI_DID_INTEL_PTL_U_H_SMBUS,
 	PCI_DID_INTEL_LNL_SMBUS,

src/soc/intel/common/block/spi/spi.c

@@ -123,6 +123,10 @@ struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_HWSEQ_SPI,
+	PCI_DID_INTEL_WCL_SPI0,
+	PCI_DID_INTEL_WCL_SPI1,
+	PCI_DID_INTEL_WCL_SPI2,
 	PCI_DID_INTEL_PTL_H_HWSEQ_SPI,
 	PCI_DID_INTEL_PTL_H_SPI0,
 	PCI_DID_INTEL_PTL_H_SPI1,

src/soc/intel/common/block/sram/sram.c

@@ -33,6 +33,8 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_SRAM,
+	PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_PTL_H_SRAM,
 	PCI_DID_INTEL_PTL_U_H_SRAM,
 	PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -425,6 +425,8 @@ struct device_operations systemagent_ops = {
 };
 
 static const unsigned short systemagent_ids[] = {
+	PCI_DID_INTEL_WCL_ID_1,
+	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,

src/soc/intel/common/block/tracehub/tracehub.c

@@ -42,6 +42,7 @@ static struct device_operations dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TRACEHUB,
 	PCI_DID_INTEL_PTL_H_TRACEHUB,
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
 	PCI_DID_INTEL_MTL_TRACEHUB,

src/soc/intel/common/block/uart/uart.c

@@ -308,6 +308,7 @@ static const char *uart_acpi_hid(const struct device *dev)
 static const char *uart_acpi_name(const struct device *dev)
 {
 	switch (dev->device) {
+	case PCI_DID_INTEL_WCL_UART0:
 	case PCI_DID_INTEL_PTL_H_UART0:
 	case PCI_DID_INTEL_PTL_U_H_UART0:
 	case PCI_DID_INTEL_LNL_UART0:
@@ -318,6 +319,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART0:
 	case PCI_DID_INTEL_CNP_H_UART0:
 		return "UAR0";
+	case PCI_DID_INTEL_WCL_UART1:
 	case PCI_DID_INTEL_PTL_H_UART1:
 	case PCI_DID_INTEL_PTL_U_H_UART1:
 	case PCI_DID_INTEL_LNL_UART1:
@@ -328,6 +330,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART1:
 	case PCI_DID_INTEL_CNP_H_UART1:
 		return "UAR1";
+	case PCI_DID_INTEL_WCL_UART2:
 	case PCI_DID_INTEL_PTL_H_UART2:
 	case PCI_DID_INTEL_PTL_U_H_UART2:
 	case PCI_DID_INTEL_LNL_UART2:
@@ -357,6 +360,9 @@ struct device_operations uart_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_UART0,
+	PCI_DID_INTEL_WCL_UART1,
+	PCI_DID_INTEL_WCL_UART2,
 	PCI_DID_INTEL_PTL_H_UART0,
 	PCI_DID_INTEL_PTL_H_UART1,
 	PCI_DID_INTEL_PTL_H_UART2,

src/soc/intel/common/block/usb4/usb4.c

@@ -52,6 +52,7 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 #endif
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA1,
 	PCI_DID_INTEL_LNL_TBT_DMA0,

src/soc/intel/common/block/usb4/xhci.c

@@ -26,6 +26,7 @@ static struct device_operations usb4_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_H_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_U_H_TCSS_XHCI,
 	PCI_DID_INTEL_LNL_TCSS_XHCI,

src/soc/intel/common/block/xdci/xdci.c

@@ -28,6 +28,7 @@ struct device_operations usb_xdci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_XDCI,
 	PCI_DID_INTEL_PTL_H_XDCI,
 	PCI_DID_INTEL_PTL_U_H_XDCI,
 	PCI_DID_INTEL_MTL_XDCI,

src/soc/intel/common/block/xhci/xhci.c

@@ -131,6 +131,7 @@ struct device_operations usb_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_XHCI,
 	PCI_DID_INTEL_PTL_H_XHCI,
 	PCI_DID_INTEL_PTL_U_H_XHCI,
 	PCI_DID_INTEL_LNL_XHCI,