soc/intel/cmn/cse_lite: Fix handling of soft disable state
When soft-disabled, boards selecting SOC_INTEL_CSE_LITE_SKU boot up
with a working state of M3_NO_UMA vs NORMAL, so handle this condition.
Without this, when vboot is not used, the board will simply fail to
boot as vboot_recovery_mode does not exist:
[ERROR] cse_lite: CSE does not meet prerequisites
[ERROR] cse_lite: Failed to get CSE boot partition info
[DEBUG] cse: CSE status registers: HFSTS1: 0x80032044,
HFSTS2: 0x32280126 HFSTS3: 0x50
[EMERG] cse: Failed to trigger recovery mode(recovery subcode:6)
This commit addresses the first error (does not meet prerequisites),
which allows CSE sync to continue and boot the RW partition in
the soft-disabled state. It also allows the CSE to properly transition
back into the normal working state (when that option is selected via
CMOS or CFR).
TEST=build/boot google/wyvern, verify able to disable/enable the ME
properly via CFR option.
Change-Id: I46da5ac248e267acee958d66ebbd97d945e722b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87517
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
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1 changed files with 3 additions and 0 deletions
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@ -267,6 +267,7 @@ static void cse_print_boot_partition_info(void)
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* - When CSE boots from RW partition (COM: Normal and CWS: Normal)
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* - When CSE boots from RO partition (COM: Soft Temp Disable and CWS: Normal)
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* - After HMRFPO_ENABLE command is issued to CSE (COM: SECOVER_MEI_MSG and CWS: Normal)
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* - When CSE boots from RW partition (COM: Soft Temp Disable and CWS: M3 w/o UMA)
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* The prerequisite check should be handled in cse_get_bp_info() and
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* cse_set_next_boot_partition() since the CSE's current operation mode is changed between these
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* cmd handler calls.
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@ -280,6 +281,8 @@ static bool cse_is_bp_cmd_info_possible(void)
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return true;
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if (cse_is_hfs1_com_soft_temp_disable())
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return true;
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} else if (cse_is_hfs1_cws_m3_no_uma() && cse_is_hfs1_com_soft_temp_disable()) {
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return true;
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}
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return false;
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}
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